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AR# 68025

UltraScale System Management Wizard: Potential for Contention between the AXI/DRP on master and I2C transactions on Slave0


When you have AXI or DRP access to the SYSMON on the Master SLR and you also have I2C enabled on the Slave SLRs, then AXI or DRP accesses on the master might not succeed under the following conditions:

  1. Accessing the AXI interface of the Master and the I2C interface of Slave0 simultaneously results in some missing AXI transactions.
  2. Similarly, performing a DRP transfer on the Master and an I2C transfer on Slave 0 causes the DRP transfer to be incomplete.

If each of these interfaces are accessed independently then this issue cannot occur.


If you are accessing the DRP port via fabric logic, you can monitor the DRDY signal to be sure that the write was successful.

When using the AXI bus, you can still get an rdvalid and wrvalid signal, but the access might not have been successful.

When writing to the registers over AXI, if you suspect this issue has occurred then you should check with a read that the previous write was performed as intended.

When reading a register over AXI, if you suspect this issue has occurred then you should build in a facility to read again.

If each of these interfaces are accessed at different times then this issue cannot occur.

AR# 68025
Date Created 10/04/2016
Last Updated 11/07/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite
  • System Monitor Wizard