When you have AXI or DRP access to the SYSMON on the Master SLR and you also have I2C enabled on the Slave SLRs, then AXI or DRP accesses on the master might not succeed under the following conditions:
If each of these interfaces are accessed independently then this issue cannot occur.
If you are accessing the DRP port via fabric logic, you can monitor the DRDY signal to be sure that the write was successful.
When using the AXI bus, you can still get an rdvalid and wrvalid signal, but the access might not have been successful.
When writing to the registers over AXI, if you suspect this issue has occurred then you should check with a read that the previous write was performed as intended.
When reading a register over AXI, if you suspect this issue has occurred then you should build in a facility to read again.
If each of these interfaces are accessed at different times then this issue cannot occur.