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AR# 68028

UltraScale Memory IP - Pulse width violations occur for designs that violate the maximum BUFGCE timing spec with the Reference Input Clock Speed (ps).

Description

Version Found: v2.1

Version Resolved: See (Xilinx Answer 58435)

The UltraScale Memory IP allows user to select the Reference Input Clock Speed (ps) based on the selected Memory Device Interface Speed (ps). 

The IP uses the maximum MMCM timing specification to create the list of available Reference Input Clock Speeds. However, because the input clock to the MMCM is driven by a BUFGCE, the maximum timing specifications of the BUFGCE should be used to limit the available input frequencies. Here is an example of the differences in timing specifications between the BUFGCE and MMCM:


 

IP that use a Reference Clock Input Speed above the allowed BUFGE Fmax will see pulse width timing violations in the timing report.

Solution

To resolve these errors, a reference clock must be selected that meets the BUFGCE Fmax datasheet specification. Future versions of the UltraScale Memory IP will adhere to the BUFGCE Fmax limits.

Revision History:

10/05/2016 - Initial Release

AR# 68028
Date Created 10/04/2016
Last Updated 10/13/2016
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
  • Virtex UltraScale+
IP
  • MIG UltraScale