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AR# 68033

FIFO Generator and Block Memory Generator IP's - Frequently Asked Questions

Description

This answer record includes a master list of Block memory generator and FIFO generator IP answer records.

Solution

(Xilinx Answer 66103)Block Memory Generator v12.0 : Width and Depth parameter settings when the BMG IP core is used in BRAM controller mode with IP Integrator flow
(Xilinx Answer 66666)2015.4 FIFO Generator: CRITICAL WARNING: [Common 17-55] warnings point to FIFO generator IP XDC file
(Xilinx Answer 66626)2015.4 How to simulate designs containing FIFO generator or Block memory generator or Distributed Memory Generator IPs in third party simulator?
(Xilinx Answer 58928)2013.3 FIFO Generator v11.0 - Create deeper or wider FIFOs using smaller size FIFOs
(Xilinx Answer 57156)FIFO Generator - Built-In Independent Clock FIFO requires RD_CLK and WR_CLK defined in Coregen GUI, why?
(Xilinx Answer 58494)Block Memory Generator 8.0 - Is it possible to view the contents of the memory in the Simulator Wave Viewer?
(Xilinx Answer 54912)Block Mem Generator v7.3 - how many clock cycles does the block RAM read port enable signal (ENB) need to assert for to read correct output values
(Xilinx Answer 46359)FIFO Generator - Built-In FIFO is not supported in Spartan architectures, only in Virtex architectures
(Xilinx Answer 43737)FIFO Generator - In Virtex-6, is Built-In FWFT mode supported?
(Xilinx Answer 38023)FIFO Generator v6.2 - asynchronous reset behavior of FIFO, and when can I start to assert write enable and read enable?
(Xilinx Answer 38219)FIFO Generator - Why does FIFO Generator core only support free-running write and read clocks?
(Xilinx Answer 38640)Block Memory Generator - What is the format of a COE file?
(Xilinx Answer 34775)FIFO generator support for non power of 2 depth
(Xilinx Answer 35350)Simulation models - What are the differences between behavioral and structural Simulation Models for FIFO and Block Memory Generator core?
(Xilinx Answer 37641)Block Memory Generator - Design Considerations for Output Register Configurations
(Xilinx Answer 35757)Distributed Memory Generator v4.1/4.2/4.3 - why does distributed RAM not have write mode settings?
(Xilinx Answer 34826)Why does width expansion of FIFO require extra gating of FIFO36 signals?
AR# 68033
Date Created 10/05/2016
Last Updated 10/14/2016
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite
IP
  • FIFO Generator
  • Block Memory Generator