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AR# 68050

Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit - Changes from rev D to rev 1.0

Description

What changes were made to the Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit between revisions D and 1.0 of the PCB?

Solution

The ZCU102 rev 1.0 changes are as follows:

  • Changed DPAUX source to PS side, remove all PL connectivity and 0 ohm resistors
  • Added 30 ohm resistors on CLK/CMD/DATA signals
  • Replaced R881 with Zero (0) ohm resistor (HDMI TX shield)
  • Replaced R882 with Zero (0) ohm resistor (HDMI RX shield)
  • Improved RTC layout, placed X5/R143/C875/C876 on bottomside near FPGA
  • Changed GTR REFLK AC capacitors to 0.01uF capacitors
  • Changed SRST_B pull-up value to 4.7K ohm
  • Changed decoupling caps on GTR MGTAVCC power rail: Added one more 1.0uF; added one more 0.47uF; added two more 0.022uF
  • Added pull-up resistors to PS_PMBUS_ALERT and PL_PMBUS_ALERT to UTIL_3V3
  • Added pull-up resistors to DAT3 signal for SD on both sides of U133; 10k ohm pull-up resistor on pin 23 and DNP on pin 15
  • Added 30 ohm resistors on MIO*_USB_DATA{7:0} and MIO58_USB_STP
  • Added jumpers for MSP430 programming: Connect MSP430_RST_B to PMOD1_0 with optional jumper; Connect MSP430_TEST to PMOD1_1 with optional jumper
  • Connected Si5324 pins 19 / 20 to GND
  • Changed silkscreen marking to Rev 1.0 and added CE mark

FMC pin changes:

FMC Clocks - HPC1ZCU102 Rev 1.0From:
Pin Type
To:
Pin Type
Update Description
FMC_HPC0_LA01_CCBank 66IOQBCSwitch with Bank 66 LA09 (a QBC pin)
FMC_HPC0_LA18_CCBank 67IOQBCSwitch with Bank 67 LA26 (a QBC pin)
FMC_HPC1_LA01_CCBank 65IOQBCSwitch with Bank 65 LA09 (a QBC pin)
FMC_HPC1_LA18_CCBank 66DBCGCSwitch with Bank 66 AA5/Y5 GC pins, re-locate HDMI_REC_CLOCK pair to Bank 65 

Detailed XDC changes:

FPGA pinFPGA PIN NameZCU102 Rev 1.0 Net NameZCU102 Rev D Net NameBank VoltageBank Number
F12IO_L6P_HDGC_50No ConnectPL_DPAUX_INVCC3V3 (3.3V)50
G11IO_L5N_HDGC_50No ConnectPL_DP_OEVCC3V3 (3.3V)50
H11IO_L5P_HDGC_50No ConnectPL_DP_HPDVCC3V3 (3.3V)50
D10IO_L4N_AD12N_50No ConnectPL_DPAUX_OUTVCC3V3 (3.3V)50
K15IO_L24N_T3U_N11_67FMC_HPC0_LA26_NFMC_HPC0_LA18_CC_NVADJ_FMC (1.8V)67
L15IO_L24P_T3U_N10_67FMC_HPC0_LA26_PFMC_HPC0_LA18_CC_PVADJ_FMC (1.8V)67
N8IO_L16N_T2U_N7_QBC_AD3N_67FMC_HPC0_LA18_CC_NFMC_HPC0_LA26_NVADJ_FMC (1.8V)67
N9IO_L16P_T2U_N6_QBC_AD3P_67FMC_HPC0_LA18_CC_PFMC_HPC0_LA26_PVADJ_FMC (1.8V)67
W1IO_L24N_T3U_N11_66FMC_HPC0_LA09_NFMC_HPC0_LA01_CC_NVADJ_FMC (1.8V)66
W2IO_L24P_T3U_N10_66FMC_HPC0_LA09_PFMC_HPC0_LA01_CC_PVADJ_FMC (1.8V)66
AC4IO_L16N_T2U_N7_QBC_AD3N_66FMC_HPC0_LA01_CC_NFMC_HPC0_LA09_NVADJ_FMC (1.8V)66
AB4IO_L16P_T2U_N6_QBC_AD3P_66FMC_HPC0_LA01_CC_PFMC_HPC0_LA09_PVADJ_FMC (1.8V)66
Y7IO_L11N_T1U_N9_GC_66FMC_HPC1_LA18_CC_NHDMI_REC_CLOCK_CC_NVADJ_FMC (1.8V)66
Y8IO_L11P_T1U_N8_GC_66FMC_HPC1_LA18_CC_PHDMI_REC_CLOCK_CC_PVADJ_FMC (1.8V)66
AC9IO_L4N_T0U_N7_DBC_AD7N_66No ConnectFMC_HPC1_LA18_CC_NVADJ_FMC (1.8V)66
AB9IO_L4P_T0U_N6_DBC_AD7P_66No ConnectFMC_HPC1_LA18_CC_PVADJ_FMC (1.8V)66
AE1IO_L24N_T3U_N11_PERSTN0_65FMC_HPC1_LA09_NFMC_HPC1_LA01_CC_NVADJ_FMC (1.8V)65
AE2IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65FMC_HPC1_LA09_PFMC_HPC1_LA01_CC_PVADJ_FMC (1.8V)65
AJ5IO_L16N_T2U_N7_QBC_AD3N_65FMC_HPC1_LA01_CC_NFMC_HPC1_LA09_NVADJ_FMC (1.8V)65
AJ6IO_L16P_T2U_N6_QBC_AD3P_65FMC_HPC1_LA01_CC_PFMC_HPC1_LA09_PVADJ_FMC (1.8V)65
AG4IO_L14N_T2L_N3_GC_65HDMI_REC_CLOCK_NNo ConnectVADJ_FMC (1.8V)65
AG5IO_L14P_T2L_N2_GC_65HDMI_REC_CLOCK_PNo ConnectVADJ_FMC (1.8V)65
N23PS_MIO39MIO39_SDIO_SELNo ConnectVCCOPS (1.8V)501
M23PS_MIO40MIO40_SDIO_DIR_CMDNo ConnectVCCOPS (1.8V)501
J24PS_MIO41MIO41_SDIO_DIR_DAT0No ConnectVCCOPS (1.8V)501
M24PS_MIO42MIO42_SDIO_DIR_DAT1_3No ConnectVCCOPS (1.8V)501

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
68042 Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit - PCB Revision Differences N/A N/A
AR# 68050
Date 03/09/2017
Status Active
Type General Article
Boards & Kits
  • Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit