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AR# 68055

Vivado Simulator 2016.3 - ERROR: [XSIM 43-4025] "<HDL file>" Line <line number>. The number of actual scalars <number>, is not the same as number of formal scalars <number>, for aggregate net <net name>

Description

Elaboration fails in Vivado Simulator 2016.3 for the following code snippet:

______
library ieee;
use ieee.std_logic_1164.all;
entity top is
end;
architecture arch of top is
signal AXIS_TINDEX: STD_LOGIC_VECTOR(9 - 1 downto 0);
begin
U3: entity work.ZAxial8Kx16LUT
port map (
ADDRB(12 downto 9) => (others => '0'),
ADDRB(8 downto 0) => AXIS_TINDEX
);
end;
____
module ZAxial8Kx16LUT (input wire [12 : 0] addrb);
endmodule
_________


It fails with the following error:


ERROR: [XSIM 43-4025] "<path>/ZAxial8Kx16LUT.v" Line 2. The number of actual scalars 22, is not the same as number of formal scalars 13, for aggregate net addrb.

The elaboration passes in previous releases.

Solution

The issue is fixed in the 2016.4 release.

To work around this issue, re-write the VHDL part as follows:


library ieee;
use ieee.std_logic_1164.all;
entity top is
end;
architecture arch of top is
signal AXIS_TINDEX: STD_LOGIC_VECTOR(9 - 1 downto 0);
signal dummy_std_logic_vector : std_logic_vector(12 downto 0);
begin
dummy_std_logic_vector <= "0000"&AXIS_TINDEX;


U3: entity work.ZAxial8Kx16LUT
port map (
ADDRB => dummy_std_logic_vector
);
end;

AR# 68055
Date 03/31/2017
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2016.3
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