General Description: When you instantiate a Pullup or Keeper for input port, FPGA Express version 3.1 connects it after IBUF instead of before IBUF. Consequently, M1 mapper optimizes them away.
This problem has gone away in FPGA Express version 3.4.
Solution
1
Use EPIC/FPGA Editor to insert desired component in the IOB.
2
Use a temporary signal to connect the Pullup, then connect this signal to the input. This solution does not work for the Keeper component.
Sample VHDL code:
Library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all;
entity pullvhd is port (A1, A2 : in std_logic; B : out std_logic); end test;
architecture RTL of pullvhd is
component PULLUP port (O : out STD_LOGIC); end component;