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AR# 68081

UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2016.3) - ERROR: [DRC 23-20] Rule violation (HDTC-6) Non-stage-one logic illegally placed - Non-stage-one logic

Description

Version Found: 4.2 (Rev2)

Version Resolved and other Known Issues: (Xilinx Answer 57945)

The following error is seen in phys_opt where logic that is replicated does not properly copy over the Tandem properties.

ERROR: [DRC 23-20] Rule violation (HDTC-6) Non-stage-one logic illegally placed - Non-stage-one logic 'c_i_wrapper_support_i/c_i_wrapper_i/inst/conf_mcap_design_switch_reg_replica' is placed at site 'SLICE_X130Y14' inside stage one Pblock 'c_i_wrapper_support_i_c_i_wrapper_i_inst_c_i_wrapper_Stage1_main'. Non-stage-one logic should not be placed inside a stage one region.

 


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)  Xilinx Solution Center for PCI Express

 

Solution

This is a known issue to be fixed in a future release of the core. To work around this issue in this Vivado release, please following the instructions below:

  • Do not run phys_opt
  • Add the appropriate Tandem constraints to the user design constraints targeting the PCIe module instance.
set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells pcie_ip_i]
set_property HD.TANDEM 1 [get_cells pcie_ip_i]

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

10/28/2016 - Initial release

AR# 68081
Date Created 10/14/2016
Last Updated 10/28/2016
Status Active
Type Known Issues
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)