UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 68086

Video Test Pattern Generator v7.0 - Maximum S_AXI "Tdata_num_bytes" Data Width Incorrectly Set

Description

When re-customizing a Test Pattern Generator instance in IP Integrator, if the maximum data width or the number of pixels per clock is changed, the byte width of the input interface is not updated.

Note that the width of tdata is set correctly, but the AXI-Stream interface width is not. This causes critical warnings when validating a block design which uses the IP.

Solution

The optional port signals width gets updated correctly, but the metadata used to populate the GUI's port signals properties are not updated.

This causes a discrepancy in the GUI, but should not cause any functional issues.

AR# 68086
Date Created 10/17/2016
Last Updated 11/01/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale+
  • More
  • Virtex UltraScale
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Less
Tools
  • Vivado Design Suite - 2016.3
IP
  • Test Pattern Generator