We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 68089

Zynq Ultrascale+ MPSoC - Which models do I use for PS DDR and PS MIO?


Which IBIS models do I use for PS DDR and PS MIO?


IBIS models are generated via the write_ibis Tcl command, specific to the design configuration used. 

For the PS portion of Zynq UltraScale+, a design must be created to configure the I/O.

To generate the IBIS model, the abbreviated flow is as follows:

  1. Open Vivado and create a new RTL design for the part/package desired.
  2. Select IP Integrator -> Create Block Design...
  3. Right-click -> Add IP... -> Zynq UltraScale+ MPSoC Processing System and double-click on new block.
  4. Configure the I/O Configuration and DDR Configuration pages to choose the specific peripherals, I/O settings, and DDR technology/topology.
  5. On the Sources tab, right-click on the block design created (default: design_1.bd) then select "Create HDL wrapper" and let Vivado manage it
  6. Select Implementation -> Run Implementation
  7. Select Implementation -> Open Implemented Design
  8. In the Tcl Console use the following command
write_ibis output.ibs

The resulting IBIS file will have the correct models associated with each PS package pin.

AR# 68089
Date 11/01/2016
Status Active
Type General Article
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ MPSoC Processing System
Page Bookmarked