IBIS models are generated via the write_ibis Tcl command, specific to the design configuration used.
For the PS portion of Zynq UltraScale+, a design must be created to configure the I/O.
To generate the IBIS model, the abbreviated flow is as follows:
- Open Vivado and create a new RTL design for the part/package desired.
- Select IP Integrator -> Create Block Design...
- Right-click -> Add IP... -> Zynq UltraScale+ MPSoC Processing System and double-click on new block.
- Configure the I/O Configuration and DDR Configuration pages to choose the specific peripherals, I/O settings, and DDR technology/topology.
- On the Sources tab, right-click on the block design created (default: design_1.bd) then select "Create HDL wrapper" and let Vivado manage it
- Select Implementation -> Run Implementation
- Select Implementation -> Open Implemented Design
- In the Tcl Console use the following command
The resulting IBIS file will have the correct models associated with each PS package pin.