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AR# 68112

UltraScale+ PCI Express Integrated Block (Vivado 2016.3) - MSI-X Vector Table and PBA

Description

Version Found: v1.1 Rev2 (Vivado 2016.3)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

The tactical patch provided with this answer record addresses issues related to MSI-X vector table and PBA.

 


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

This is a known issue to be fixed in a future release of the core, please install the tactical patch attached as described below:

METHOD 1:

  1. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist)
  2. Extract the contents of the ".zip" archive to a directory starting with the name AR68112.
    Note: most extraction tools will allow you to automatically create a directory with the same name as the zip file
  3. Run Vivado software tools from the original install location.

 

METHOD 2:

  1. Create a separate directory for the patched files
  2. Extract the contents of the ".zip" archive to the desired patch directory location
  3. Set the MYVIVADO environment variable to point to the Vivado directory under this patch directory
    For example:
    set MYVIVADO=C:\MYVIVADO\vivado-patch-AR68112\vivado\
  4. Run Vivado software tools from the original install location.

 

Note: The "Version Found" column lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions. This is an issues with latency of the core.

Revision History:

10/30/2016 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR68112_Vivado_2016_3_preliminary_rev1.zip 1 MB ZIP
AR# 68112
Date Created 10/20/2016
Last Updated 11/07/2016
Status Active
Type Known Issues
IP
  • UltraScale+ FPGA Integrated Endpoint Block for PCI Express