This answer record provides Integrated Debugging Features and Usage Guide for UltraScale and UltraScale+ FPGA Gen3 Integrated Block for PCI Express cores in a downloadable PDF to enhance its usability.
Answer Records are Web-based content that are frequently updated as new information becomes available. Visit this answer record to obtain the latest version of the PDF.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
The document attached with this answer record describes the new integrated Ease-of-Use features added in Vivado 2016.3 for UltraScale and UltraScale+ FPGA Gen3 Integrated Block for PCI Express cores. The features are covered in detail with screenshots to make it easier for users to understand its implementation and usage.
Prior to the Vivado 2016.3 release, a manual insertion of ILA core was required to probe signals and find out the LTSSM transitions during the link training process.
To do an eye scan of a PCI Express link, users had to opt for a manual approach such as the reference design provided in XAPP1198.
Another major issue in debugging PCI express issues in UltraScale devices was interpreting the scrambled data on a PIPE interface.
All of these difficulties have been addressed in the Vivado 2016.3 release of UltraScale and UltraScale+ PCI Express cores. The core configuration now comes with the following three integrated debug options.
11/20/2016 - Initial release
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