When a burst transaction issues from AXI-4 Memory Mapped Interfaces, the first write to the memory will be issued twice to the same address.
This behavior impacts on the Micron BPI flash.
According to the behavior guidelines from Micron, if a write is performed to the same address twice, the second write will be ignored and the first written data will not be broken.
However, this will cause an internal PROGRAM Error, and afterwards write is unavailable until this error bit is cleared.
This is a known issue discovered in version 3.0 of the core that is planned to be resolved in a future release of the core.
In the meantime, the work-around is to use a single AXI-4 transaction.
Using AXI-4 burst write transactions does not help much when improving flash programing because the bottleneck is on the flash memory side.
As the screen capture above shows, the core de-asserts the WREADY for a long cycle to delay the write transaction from the AXI-4 master.
The following table is from the Micron BPI datasheet:
Using Buffered Programing mode, and filling in 512 words of one buffer with a single AXI-4 transaction can also improve programming timing.