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AR# 68143

DDR4 IP - IP GUI hangs and crashes for specific settings

Description

Version Found: v2.1

Version Resolved: See (Xilinx Answer 58435)

The DDR4 IP GUI has been seen to hang and crash when the following settings are used:

  • Targeting an XCZU7E-FFVC1156-i-1 FPGA device
  • DDR4 component device is used
  • "Chip Select" is disabled
  • The DRAM width is changed to 16 (hang occurs here)

Solution

To fix this issue an IP patch must be installed. To install the patch, extract the contents of "AR68143_Vivado_2016_3_preliminary_rev1.zip" to the 2016.3 install directory (for example, C:\Xilinx\Vivado\2016.3\), then open Vivado 2016.3 and generate the DDR4 IP.

Note: This tactical patch is only compatible with the Vivado 2016.3 and DDR4 IP v2.1.

Revision History:

11/01/2016 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR68143_vivado_2016_3_preliminary_rev1.zip 16 MB ZIP
AR# 68143
Date Created 10/27/2016
Last Updated 11/02/2016
Status Active
Type Known Issues
Devices
  • Zynq UltraScale+ MPSoC
IP
  • MIG UltraScale