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AR# 68143

UltraScale+ MPSoC DDR4 - Tactical Patch - IP GUI hangs and crashes for specific settings

Description

Version Found: v2.1

Version Resolved: See (Xilinx Answer 69035)

The DDR4 IP GUI has been seen to hang and crash when the following settings are used:

  • Targeting an XCZU7E-FFVC1156-i-1 FPGA device
  • DDR4 component device is used
  • "Chip Select" is disabled
  • The DRAM width is changed to 16 (a hang occurs here)

Solution

To fix this issue an IP patch must be installed. To install the patch, extract the contents of "AR68143_Vivado_2016_3_preliminary_rev1.zip" to the 2016.3 install directory (for example, C:\Xilinx\Vivado\2016.3\), then open Vivado 2016.3 and generate the DDR4 IP.

Note: This tactical patch is only compatible with the Vivado 2016.3 and DDR4 IP v2.1.

Revision History:

11/01/2016 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR68143_vivado_2016_3_preliminary_rev1.zip 16 MB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 68143
Date 12/21/2017
Status Active
Type Known Issues
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.4
IP
  • MIG UltraScale
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