UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 68164

High Speed SelectIO Wizard - Resets When Controlling en_vtc_bsc(7:0) can restart the reset sequence

Description

Version Found: 2016.2 and older

When using High Speed SelectIO Wizard (HSSIO) the BSC_EN_VTC can restart the reset sequence. 

The problem can occur when using the following inputs for the HSSIO IP core after the reset state machine has completed the reset process (RST_SEQ_DONE = 1):

  • en_vtc_bsc7
  • en_vtc_bsc6
  • en_vtc_bsc5
  • en_vtc_bsc4
  • en_vtc_bsc3
  • en_vtc_bsc2
  • en_vtc_bsc1
  • en_vtc_bsc0

Note: this Answer Record should not be viewed in isolation. 

For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)

Solution

This issue is resolved in the 2016.3 version of the High Speed SelectIO Wizard.

For older designs using Vivado 2016.2 and earlier, the reset state machine can be fixed by editing the Verilog RTL for the reset state machine.

The reset state machine RTL that causes the reset sequence to restart is defined in rst_scheme.v.

           RESET_SEQ_DONE:
           begin
             
              if (!pll0_locked_sync || (USE_PLL1 == 1'b1 && !pll1_locked_sync ) || !all_bsc_dly_rdy || !all_bsc_vtc_rdy )
                 hssio_state        <= `pTCQ ASSERT_ALL_RESETS;
              else begin
                 rst_seq_done       <= `pTCQ 1'b1;
                 hssio_state        <= `pTCQ RESET_SEQ_DONE;
              end
AR# 68164
Date Created 11/02/2016
Last Updated 11/07/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
  • Virtex UltraScale+