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AR# 68166

Zynq UltraScale+ MPSoC - PS-PL AXI widths not configured in 2016.3 FSBL

Description

When using an AXI interface with 32 or 64-bit width (or 128-bits for M_AXI_HP0_LPD) and using FSBL to initialize the system, bus width is not configured causing data corruption.

Solution

Although this issue was resolved in the 2016.3 release for the Tcl initialization workflow (See (Xilinx Answer 66295)), remains in the FSBL workflow because it uses its own PS-PL isolation removal function, rather than psu_ps_pl_isolation_removal_data().

The current work-around is to include the psu_ps_pl_isolation_removal_data function in the FSBL initialization process:

u32 XFsbl_HookPsuInit(void)
{
u32 Status = XFSBL_SUCCESS;

/* Add the code here */

Status = (u32)psu_init();

if (XFSBL_SUCCESS != Status) {
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_PSU_INIT_FAILED\n\r");
/**
* Need to check a way to communicate both FSBL code
* and PSU init error code
*/
Status = XFSBL_PSU_INIT_FAILED + Status;
}

/* AFI Configuration workaround */
psu_ps_pl_isolation_removal_data();

return Status;
}

This issue will be fixed in the 2016.4 release.

AR# 68166
Date 12/21/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.3
IP
  • Zynq UltraScale+ MPSoC Processing System
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