Xilinx is updating Kintex UltraScale FPGA and Virtex UltraScale FPGA Vivado Speed Files for certain SelectIO primitive pin timing and skew checks.
Designs using memory interfaces and/or SelectIO applications in Native and Component mode are required to be re-timed and any timing violations need to be corrected.
Examples of affected IP cores are:
The following timing parameters have been updated in the Speed File:
New designs must be generated using Vivado 2016.4 or later.
Existing designs must be re-timed using the new speed files and updates made as necessary. If no timing violations occur, designs do not need to be updated.
To do this, follow the steps below:
1) Re-run timing analysis
2) If timing violations occur, please review the following:
If you encounter both skew and setup/hold errors, address the OSERDES skew first.
If you encounter setup/hold errors, address this next.