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Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs
Xilinx is updating Kintex UltraScale FPGA and Virtex UltraScale FPGA Vivado Speed Files for certain SelectIO primitive pin timing and skew checks.
Designs using memory interfaces and/or SelectIO applications in Native and Component mode are required to be re-timed and any timing violations need to be corrected.
Examples of affected IP cores are:
- MIG (DDR3, DDR4, RLDRAM3, QDRII+, QDRIV)
- NAND Flash
- 1000 BaseX
The following timing parameters have been updated in the Speed File:
- OSERDESE3 skew between CLK and CLKDIV inputs
- ISERDESE3 skew between CLK and CLK_B inputs
- IDDRE1 skew between C and CB inputs
- BITSLICE_CONTROL skew between RIU_CLK and PLL_CLK inputs. For further information see (Xilinx Answer 68266)
- Only applies to DDR3, DDR4, and RLDRAM3 interfaces
- BITSLICE_CONTROL, RXTX_BITSLICE, RX_BITSLICE, TX_BITSLICE, ISERDESE3, IDELAYE3, and ODELAYE3 pin timing parameters
New designs must be generated using Vivado 2016.4 or later.
Existing designs must be re-timed using the new speed files and updates made as necessary. If no timing violations occur, designs do not need to be updated.
To do this, follow the steps below:
1) Re-run timing analysis
- Install Vivado 2016.4 and re-run timing on the existing design
- If no timing violations occur, designs do not need to be updated
2) If timing violations occur, please review the following:
- If Max Skew (Pulse Width) timing violations occur:
- If setup or hold time violations occur, see (Xilinx Answer 68267) for further information
If you encounter both skew and setup/hold errors, address the OSERDES skew first.
If you encounter setup/hold errors, address this next.
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- Kintex UltraScale
- Virtex UltraScale