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AR# 68172

2016.3: FIFO Generator v13.0 - Empty flag does not de-assert after reset in Asynchronous FWFT FIFOs


In the FIFO Generator core, an empty flag does not de-assert after reset in Asynchronous First Word Fall Through (FWFT) FIFOs for the following configuration:

  1. Number of synchronization stages=8
  2. wr_clk to rd_clk frequency ratio is >=4
  3. Safety circuit is enabled


This is a known issue when the FIFO Generator core is configured with Independent clock FIFOs and the above configuration.

To work around this issue:

  1. Reduce the number of synchronization stages
  2. Reduce the write to read clock frequency ratio
  3. Disable the "Enable Safety Circuit" option

This issue is scheduled to be fixed in the Vivado 2017.1 release.

AR# 68172
Date 11/07/2016
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2016.3
  • FIFO Generator
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