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AR# 68191

Zynq-7000 - Random long interrupt latencies or peripheral access times


When using the standalone BSP or an Operating System which uses it (such as FreeRTOS), accesses during synchronization barriers and other peripheral accesses can take multiple uS to complete with no obvious cause.

What could cause this behavior?


To support execution from QSPI (via execute-in-place) or external SMC devices, these peripherals are by default marked as "Normal" memory in the standalone BSP translation_table.S:

.rept 0x0020                  /* 0xe4000000 - 0xe5ffffff (SRAM) */
.word SECT + 0xc0e            /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
.set SECT, SECT+0x100000
.rept 0x0020                  /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
.word SECT + 0xc0a            /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
.set  SECT, SECT+0x100000

However, a side-effect of this memory setting is that speculative accesses can occur to these peripherals, even if unused. 

During speculative accesses, a memory barrier or other peripheral access might be stalled until this slow access completes.

To resolve this issue, consider changing these memory ranges to device-type memory:

#include "xil_mmu.h"
#include "xparameters_ps.h"
    /* Xilinx Answer 68191: 0xe4000000 - 0xe5ffffff (SRAM) */
    for(int i=0; i < 0x20; i++) {
        Xil_SetTlbAttributes(XPS_PARPORT1_BASEADDR + i*0x100000,0xc06);
    /* Xilinx Answer 68191: 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
    for(int i=0; i < 0x20; i++) {
        Xil_SetTlbAttributes(XPS_QSPI_LINEAR_BASEADDR + i*0x100000,0xc06);

For more information, see (Xilinx Answer 52486). As of this writing, the Zynq UltraScale+ translation table marks these regions as Device ranges, and so is currently unaffected.

AR# 68191
Date 11/14/2016
Status Active
Type General Article
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.2
  • Processing System 7
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