AR# 68211

Zynq UltraScale+ MPSoC - FSBL does not initialize above first 2GB of PS DDR when using ECC, causing program exceptions

Description

The FSBL does not initialize above the first 2GB of PS DDR when using ECC, which causes program exceptions.

How do I resolve this issue?

Solution

This issue is planned to be fixed in the FSBL starting in Vivado 2016.4.

AR# 68211
Date 12/12/2016
Status Active
Type General Article
Devices
Tools
IP