UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 68211

Zynq UltraScale+ MPSoC - FSBL does not initialize above first 2GB of PS DDR when using ECC, causing program exceptions

Description

The FSBL does not initialize above the first 2GB of PS DDR when using ECC, which causes program exceptions.

How do I resolve this issue?

Solution

This issue is planned to be fixed in the FSBL starting in Vivado 2016.4.

AR# 68211
Date Created 11/10/2016
Last Updated 11/24/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
Tools
  • Vivado Design Suite - 2016.3
IP
  • Zynq UltraScale+ MPSoC Processing System