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AR# 68237

2016.x/2017.1 Zynq UltraScale+ MPSoC - QSPI programming requires the QSPI Feedback Clock on MIO6


QSPI programming (for example on a ZCU102 board) requires that the FSBL be generated with the QSPI Feedback Clock enabled.

This applies to Zynq UltraScale+ devices booting in JTAG mode from both XSDK and Vivado Hardware Manager.


The 2016.x and 2017.1 versions of the QSPI Programmer probe the flash at 60MHz, and fail if the QSPI Feedback clock is NOT enabled in the Hardware configuration used to build the FSBL.

In a future release (2017.3) the probing will be performed at lower frequencies (<40MHz) and the QSPI Feedback clock will not be a requirement for programming.

AR# 68237
Date 04/19/2017
Status Active
Type General Article
  • Zynq UltraScale+ MPSoC
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.4
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