I have a Tcl script using a basic non-project flow to compile and implement an IP Integrator Block Design (BD).
The script ran successfully in Vivado 2016.2. Then after moving to Vivado 2016.3 and upgrading all of the IP blocks of the BD as required, my script fails in synthesis with errors similar to the following:
There appears to be an error for every block in the design.
I look in the BD directory and the output products for all of the IP blocks appear to have been successfully generated.
What changed between Vivado 2016.2 and 2016.3?
Am I missing a step?
Do I need to add these subcores individually?
In Vivado 2016.3 there was a change to the default BD generation mode. The default was changed from Global to Out of Context (OOC) per IP.
You will not typically see this problem when migrating an existing project because the migration script will maintain the existing generation mode setting. However, in a scripted flow where the entire project or design is being recreated, the new default settings would apply unless explicitly changed.
Additionally, the "OOC per IP" BD generation is not allowed in non-project mode.
Therefore, starting in Vivado 2016.3, if you are using a scripted non-project mode, you will need to set the BD generation back to global.
To do this, set the synth_checkpoint_mode to None (Global synthesis) before generating targets.
set_property synth_checkpoint_mode None [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd]
generate_target all [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd]