We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 68275

2016.4 Vivado IP Flows - After migrating a synthesized design to Vivado 2016.3, the OOC run of some IP of a Block Design are reset when launching implementation


I have a project which was created prior to Vivado 2016.3.

The Project contains a Block Design (BD) and all of the output products of the BD in the project are generated Out-of-Context (OOC) per IP. Synthesis has completed without error.

However, when I open the project in Vivado 2016.3 and launch implementation, some OOC sub-runs of the BD are reset, even though the IP is locked and not upgraded. 

Eventually implementation fails for lack of DCP.


It has been discovered that under certain cases the run of a sub-IP of an hierarchical IP will be forced to re-run even if the top level IP core is locked.

The issue occurs because the Vivado Run Scheduler (VRS) is seeing a dependency between the implementation run and the OOC runs.

Even though synthesis of the run was completed in the earlier version of Vivado, skipping synthesis in Vivado 2016.3 and running implementation causes Vivado to schedule un-needed out-of-context synthesis runs.

Then for locked IP, the OOC synthesis will fail because the IP is locked. 

If you encounter this problem, you will need to generate the IP core and run top level synthesis with the IPs current version, or bring in the completely synthesized DCP to Vivado 2016.3 for implementation.

The issue is scheduled to be fixed in Vivado 2017.1.

AR# 68275
Date 12/19/2016
Status Active
Type Known Issues
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.4
Page Bookmarked