In cores supporting the 24,330.24 Mbps line rate, scrambling is not supported at the 8B10B encoded line rates:
This is a known issue in the CPRI v8.7 (Rev 1) core, included in the Vivado 2016.4 release. It will be fixed in the 2017.1 release.
It affects the cores supporting the 24,330.24 Mbps line rate only.
To work around this issue, generate CPRI with a different line rate if you want to enable scrambling at 8b10b encoded line rates, or contact Xilinx Technical Support for further assistance.
For a detailed list of CPRI known issues, see (Xilinx Answer 54473)