AR# 68530

CPRI v8.7 (Rev 1) - For some UltraScale and UltraScale+ devices, the RX and TX output clocks are not correctly constrained if cores are generated with the 9.830G and under line rate option.

Description

The information in this Answer Record applies to UltraScale and UltraScale+ devices with the following speed grades:

  • -3
  • -2
  • -2L
  • -2LV
  • -1H
  • -1HV

Cores generated with the 9.830G and under line rate option will not be correctly constrained. 

The RX and TX output clocks from the transceiver are constrained to 153.6MHz instead of the required 245.76MHz.

Solution

This is a known issue in the CPRI v8.7 (Rev 1) core, included in Vivado v2016.4. A fix for this issue will be provided in the 2017.1 release.

The constraints on RX and TX output clocks from the transceiver should be overridden in the users XDC file. 

For example:

create_clock -period 4.069 -name recclk [get_pins -hier -filter {name =~ *rxusrclk_bufg0/O}]
create_clock -period 4.069 -name coreclk [get_pins -hier -filter {name =~ *txusrclk2_bufg0/O}]

rxusrclk_bufg0 and txusrclk2_bufg0 in the above constraints are the BUFG_GT clock buffers for the transceiver RX and TX output clocks.

AR# 68530
Date 01/17/2017
Status Active
Type General Article
IP