2. Support
  3. AR# 6858: PROM XC18V00 - What is the Security (Read Protect) option and how is it selected?
  4. AR# 68582: Zynq UltraScale+ MPSoC: 2016.4 FSBL hangs when PS DDR ECC is enabled

AR# 68582

Zynq UltraScale+ MPSoC: 2016.4 FSBL hangs when PS DDR ECC is enabled

Description

Starting in Vivado 2016.4, the upper 2GB DDR initialization is added when ECC is enabled.

However FSBL hangs due to this function. How do I prevent the hang from occurring?

Solution

This occurs because of an issue in Windows where all the 64-bit addresses are truncated to 32-bit (PCIe, DDR) in xparameters.h, leading the FSBL to hang during the upper DDR ECC initialization.

Linux hosts are not affected.

The work-around is to manually modify the xparameters.h as follow:

 

Before:

/* Definitions for peripheral PSU_DDR_1 */
#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x00000000
#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x7FFFFFFF
 

After:

/* Definitions for peripheral PSU_DDR_1 */
#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000
#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF

This issue is fixed in Vivado 2017.1 and later versions.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
68211 Zynq UltraScale+ MPSoC - FSBL does not initialize above first 2GB of PS DDR when using ECC, causing program exceptions N/A N/A
AR# 68582
Date 05/04/2017
Status Active
Type General Article
Devices
Tools