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AR# 68617

DMA Subsystem for PCI Express (Vivado 2016.4) - x16 lane support in VCU118 (xcvu9p-flga2104 -2L device)

Description

Version Found: 3.0 (Rev 1)

Version Resolved and other Known Issues: (Xilinx Answer 65443)


When configuring the DMA Subsystem for PCI Express core for VCU118 board (xcvu9p-flga2104 -2L device),  the maximum link width supported is limited to x8. 


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

This is a known issue, which is due to be fixed in a future release of the core.

To work around the issue, when configuring the DMA Subsystem for PCI Express core for a VCU118 board, follow the steps below:

  1. Skip the selection in the 'board' tab (do not select anything apart from custom)
  2. On the Basic tab, select PCIe block X1Y2 and required link width x16

To use this work-around, the following constraints must be applied:

use set_property -dict [list CONFIG.vcu118_board {true}] [get_ips <component_name>]


Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

02/03/2017 - Initial release

AR# 68617
Date 02/15/2017
Status Active
Type Known Issues
IP
  • DMA for PCI Express (PCIe) Subsystem
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