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AR# 68675

How do I use the UltraScale+ GTY FPLL with IBERT

Description

To use the FPLL in UltraScale+ GTY the Tcl commands below need to be run.

Follow these steps:

  1. Build an IBERT for the desired line rate, and make sure it uses the closest refclk selection to the one required.
  2. Edit the Tcl script with the integer part and fractional part of the feedback divider that you need. See below for a description of these edits.
  3. Set your refclk up on your board
  4. Load the IBERT bitstream
  5. Source the edited Tcl script (from the contents below) which includes resetting all of the PLLs.
  6. Do the usual TX reset, RX reset and IBERT reset in the IBERT GUI.

Solution

# script to set a fractional 82.5 at runtime to the QPLL0 FBDIV of all QPLL0 found in an IBERT

set_property PORT.SDM0DATA 0800000 [get_hw_sio_commons]

set_property DRP.QPLL0_SDM_CFG0 0000 [get_hw_sio_commons]

set_property DRP.QPLL0_FBDIV 50 [get_hw_sio_commons]

commit_hw_sio [get_hw_sio_commons]

set_property PORT.QPLL0RESET 1 [get_hw_sio_commons]

commit_hw_sio [get_hw_sio_commons]

after 50

set_property PORT.QPLL0RESET 0 [get_hw_sio_commons]

commit_hw_sio [get_hw_sio_commons]


Tcl script editing instructions:

The line below sets the numerator of the fractional part:

set_property PORT.SDM0DATA 0800000 [get_hw_sio_commons]

If this value is 0.5, 0400000 would be 0.25 and so on. Edit this line to set the fractional part to what you need.

The line below sets the integer part of the feedback divider:

set_property DRP.QPLL0_FBDIV 50 [get_hw_sio_commons]

The integer part of the feedback divider is in hex and you add two to the value to get the actual divide value the hardware implements, so the actual value of the divider here is 82 decimal.

The combined settings in the attached script are 82.5 decimal.


If you do not wish to apply the same fractional setting to all lanes in your IBERT then you will need to edit this script to only change the lanes you need the fractional setting on.

AR# 68675
Date 04/19/2017
Status Active
Type General Article
Devices
  • FPGA Device Families
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