UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 68690

Xilinx Vivado Implementation Solution Center - phys_opt_design Design Assistant

Description

phys_opt_design - Design Assistant

Note: This article is part of the Xilinx Vivado Implementation Solution Center (Xilinx Answer 68350) is available to address all questions related to Vivado Implementation.

Whether you are starting a new design with Vivado Implementation or troubleshooting a problem, use the Vivado Implementation Solution Center to guide you to the right information.

Solution


Functionality and Usage:
(Xilinx Answer 53986)2012.x Vivado Timing Closure Suggestion - What is 'phys_opt' command?

Debugging Tips

High Frequency Issues & Design Advisories:

(Xilinx Answer 68081)UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2016.3) - ERROR: [DRC 23-20] Rule violation (HDTC-6) Non-stage-one logic illegally placed - Non-stage-one logic
(Xilinx Answer 68571)2015.4 Vivado - Phys_opt_design inverts ENBWREN of RAMB36E1 connection, causing BRAM function error.
AR# 68690
Date 04/06/2017
Status Active
Type Solution Center
Tools
  • Vivado Design Suite
Page Bookmarked