AR# 68691


Xilinx Vivado Implementation Solution Center - route_design Design Assistant


route_design - Design Assistant


Note: this article is part of the Xilinx Vivado Implementation Solution Center (Xilinx Answer 68350)

The Xilinx Vivado Implementation Solution Center is available to address all questions related to Vivado Implementation.

Whether you are starting a new design with Vivado Implementation or troubleshooting a problem, use the Vivado Implementation Solution Center to guide you to the right information.


Functionality and Usage

(Xilinx Answer 54683) 2012.4 Vivado Implementation Tools - How do I do manual routing in Vivado GUI?
(Xilinx Answer 67548) ECO : Next Generation FPGA Editor
(Xilinx Answer 59242) How do I use Vivado's Directed Routing features to lock down my critical paths?
(Xilinx Answer 61449) Vivado Implementation - why has route_design created a long route for a net which has a setup violation?
(Xilinx Answer 66698) Vivado Implementation Using congestion metrics to find high fanout nets

Debugging Tips

(Xilinx Answer 66314) Vivado Congestion
(Xilinx Answer 66823) Vivado - Overcoming routing issues with unroutable connectivity

High Frequency Issues & Design Advisories

(Xilinx Answer 69152) Design Advisory 2017.1 Tactical Patch for Vivado bi-directional logic issue using component mode primitives (IOBUF usage with IDDRE1, ISERDESE3, ODDRE1, OSERDESE3, or FDCE/FDPE/FDRE/FDSE with IOB=TRUE)
(Xilinx Answer 67511) Design Advisory Tactical Patch for Device Model Inversion
AR# 68691
Date 10/02/2017
Status Active
Type Solution Center
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