AR# 68716


LogiCORE IP Video Processing Subsystem (VPSS) v2.0 - Why do I see timing failures due to too many layers of logic?


When you are creating a design using the LogiCORE IP Video Processing Subsystem instantiated in one IP Integrator Block Diagram (BD) file, and your clock creation blocks are in an RTL or a different BD file, it is possible to have the clock in the VPSS BD file assigned to the default frequency instead of the desired frequency. 

This can result in the Video Processing Subsystem synthesizing for a lower than expected clocking frequency which will result in timing failures after synthesis or implementation.


Make sure the clock port in the IP Integrator BD file containing the Video Processing Subsystem instance is assigned to the desired operating frequency.

You can check this by double clicking on the input clock port in your BD to check the frequency property.

The default frequency for a clock port in IP Integrator is 100MHz as shown in the screenshot below:

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AR# 68716
Date 08/15/2017
Status Active
Type General Article
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