UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 68778

Vivado Simulator - No ports or signals are dumped to SAIF file when the entity is instantiated inside a generate block

Description

I am trying to log SAIF for the ports of an entity that is used in generate blocks.

For example:

g_sdi : for i in 0 to 1 generate
      u_sdi : entity work.sdi
      generic map(
      xxx
      )
      
      port map(
       xxx
       );
     end generate

However, no ports are written to the SAIF file.

Solution

This is a tool issue and will be fixed in the 2017.1 release.

The current work-around is to unroll the for loop:

      u_sdi_0 : entity work.sdi
      generic map(
      xxx
      )
      
      port map(
       xxx
       );



      u_sdi_1 : entity work.sdi
      generic map(
      xxx
      )
      
      port map(
       xxx
       );

AR# 68778
Date 04/18/2017
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2016.4
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.2
  • More
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2015.4.2
  • Vivado Design Suite - 2015.4.1
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Less
Page Bookmarked