General Description: How to infer the BUFGDLL cell for Virtex using the xc_clockbuftype attribute?
A Virtex only attribute, first introduced in Synplify 5.1.2, which specifies that a clock port is to use the BUFGDLL macro.
The BUFGDLL is a special purpose clock delay locked loop buffer for clock skew management. It is provided as a user convenience for the most frequently used configuration of elements for clock skew management. It consists of an IBUFG followed by a CLKDLL followed by a BUFG.
always @(posedge clk or posedge rst) if (rst) q <= 2'b0; else q <= d;
-- VHDL library IEEE;
library IEEE; use IEEE.std_logic_1164.all; library synplify; use synplify.attributes.all;
entity bufgdll_ex1 is port (D : in STD_LOGIC_VECTOR (1 downto 0); CLK, RST : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (1 downto 0)); attribute xc_clockbuftype of CLK : signal is "BUFGDLL"; end bufgdll_ex1;
architecture XILINX of bufgdll_ex1 is
process (RST, CLK) begin if (RST = '1') then Q <= "00"; elsif rising_edge(CLK) then Q <= D; end if; end process;