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AR# 68804

LogiCORE IP JESD204C - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the JESD204C LogiCORE IP and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2017.1 (beta) and newer tools.

For Known Issues within JESD204B, please visit (Xilinx Answer 54480) JESD204B - LogiCORE IP Release Notes and Known Issues for Vivado 2013.1 and newer tools.

JESD204 LogiCORE IP Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-jesd204.html


Xilinx Forums:

Please seek technical support via the Networking And Connectivity Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.


Alternatively, see the Change Log Answer Records:

Answer RecordTitle
(Xilinx Answer 71806)2018.3 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 71212)2018.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 70699)2018.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 70386)2017.4 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 69903)2017.3 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 69326)2017.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 69055)2017.1 Vivado IP Release Notes - All IP Change Log Information


For any Transceiver related questions or issue, please see the table below.

Answer RecordTitle
(Xilinx Answer 41613)7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List
(Xilinx Answer 57487)UltraScale FPGA Transceiver Wizard - Release Notes and Known Issues for Vivado 2013.4 and newer versions
(Xilinx Answer 62670)UltraScale FPGAs GTH Transceiver - Known Issues and Answer Record List
(Xilinx Answer 64440)UltraScale FPGA GTY Transceiver - Known Issues and Answer Record List
(Xilinx Answer 64838)Design Advisory for UltraScale FPGA Transceivers Wizard: GTH Production Updates in Vivado 2015.2


Version Table


This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v4.12019.1
v4.0(Rev. 1)2018.3.1
v4.02018.3
v3.0(Rev. 1)2018.2
v3.02018.1
v2.0(Rev.1)2017.4
v2.02017.3
v1.0 (Rev. 1)2017.2
v1.0 (beta)2017.1


General Guidance

No guidance at this time.


Known and Resolved Issues

The following table provides known issues for the LogiCORE IP JESD204C core, starting with v1.0, initially released in Vivado 2017.1 (beta).

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 72355)JESD204 - 2019.1 - Architecture limitationsv4.1
(Xilinx Answer 69021)JESD204 - 2017.1 - UltraScale / UltraScale+ IBUFDS_GTE output instability

Revision History

05/13/2019Updated for 2019.1 release
12/13/2018Updated for 2018.2,2018.3 release
12/13/2018Updated for 2017.4,2018.1 release
10/10/2017Updated for 2017.3 release
03/03/2017Initial Release
11/04/2017Updated for 2017.1 release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
67698 JESD204 Solution Center - Top Issues and Frequently Asked Questions N/A N/A

Child Answer Records

AR# 68804
Date 05/29/2019
Status Active
Type General Article
Tools
IP
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