AR# 68819

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Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit - Known Issues and Release Notes Master Answer Record

Description

This Answer Record lists all known issues associated with the Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit.

Solution

Zynq UltraScale+ MPSoC Related Issues


(Xilinx Answer 64375) Xilinx UltraScale+ MPSoC Solution Center
(Xilinx Answer 65467) Zynq UltraScale+ MPSoC Boot and Configuration 
(Xilinx Answer 66194) Zynq UltraScale+ MPSoC Processing System (PS) DDR Controller


Board / Kit Related Issues


(Xilinx Answer 70515) ZCU102; ZCU106HDMI Transmitter Subsystem - Why do I have problems with connecting to some HDMI Sinks?
(Xilinx Answer 70686) ZCU102/ZCU104/ZCU106 Strap work-around for getting stable PHY link when used in RGMII or SGMII mode
(Xilinx Answer 69493) Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit - Reprogramming the Maxim Integrated Power Controllers
(Xilinx Answer 71961) Zynq UltraScale+ MPSoC ZCU102 and ZCU106 Evaluation Kits - DDR4 SODIMM change


Documentation Related Issues


(Xilinx Answer 71127) Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit - Pin mapping in Vivado 2018.1 board file part0_pins.xml is incorrect
(Xilinx Answer 70514) HDMI Transmitter and Receiver Subsystem - Where can I find an HDMI Compliant Reference Schematic?


IP Related Issues


(Xilinx Answer 61625) Video IP Example Design Landing Page
(Xilinx Answer 70014) 2017.3 Zynq UltraScale+ MPSoC VCU: Multistream decoder > 4 FULL HD instance fails with memory allocation errors in Linux
(Xilinx Answer 71021) 2018.1/2 Zynq UltraScale+ MPSoC VCU: Why do I see frame drops at bitrates > 500Mbps when using GStreamer?
(Xilinx Answer 70013) 2017.3 Zynq UltraScale+ MPSoC VCU: Frame drops are observed in 4kp60fps transcode use case in Linux
(Xilinx Answer 70182) 2017.3 IP Flows - Synthesis fails on Video Mixer IP in Block Design; "Synthesis target needs to be generated before calling compile_c."
(Xilinx Answer 69447) Zynq UltraScale+ MPSoC - PS SMMU cannot distinguish between multiple masters connected to a single PS port through SmartConnect
(Xilinx Answer 70959) 2018.1 Zynq UltraScale+ MPSoC VCU: Frame drops are observed with 4kp60fps live source gstreamser pipeline in Linux
(Xilinx Answer 71026) LogiCORE H.264/H.265 Video Codec Unit (VCU) v1.0 - Why does the BVALID fail to de-assert and the BRESP fail to assert when doing back-to-back writes to the VCU, which can result in a VCU Hang?


Design Tools Related Issues


(Xilinx Answer 67156) PetaLinux 2016.1 - Product Update Release Notes and Known Issues
(Xilinx Answer 69074) PetaLinux 2017.1 - Product Update Release Notes and Known Issues
(Xilinx Answer 69372) PetaLinux 2017.2 - Product Update Release Notes and Known Issues
(Xilinx Answer 70187) 2017.2 ZCU106 VCU TRD - How do I force my DisplayPort monitor to connect at 4Kp30 (3840x2160p30) and launch the TRD GUI?
(Xilinx Answer 69978) Zynq UltraScale+ MPSoC: How to enable UHS (SD 3.0) support for ZCU102 and ZCU106 evaluation board PetaLinux BSPs
(Xilinx Answer 70062) 2017.3 Zynq UltraScale+ MPSoC: How to enable UHS (SD 3.0) support in Standalone Driver for ZCU102 and ZCU106 evaluation board
(Xilinx Answer 70956) 2018.1 Zynq UltraScale+ MPSoC: XEN boot fails with pre-built images for ZCU106 PetaLinux BSP
(Xilinx Answer 71163) 2017.3/4 Zynq UltraScale+ MPSoC VCU: GStreamer OMX H.264 decoder timeout when transition from GST_STATE_PLAY to GST_STATE_NULL
(Xilinx Answer 71167) 2018.1/2Zynq UltraScale+ MPSoC Video Codec Unit (VCU) - How do I build gst-shark for latency measurements?
(Xilinx Answer 71382) 2018.1/2 Zynq UltraScale+ MPSoC Video Codec Unit (VCU) - TRD Design Module does not build with PetaLinux SDK generation
(Xilinx Answer 71381) 2018.1/2 Zynq UltraScale+ MPSoC Video Codec Unit (VCU) - TRD Design Module 3 does not build when using BB_NO_NETWORK (without network)
(Xilinx Answer 70907) 2018.1 Vivado Constraints[DRC BIVB-1] Bank I/O standard Support: Bank 65 has incompatible IO
(Xilinx Answer 70063) SMPTE UHD-SDI RX Subsystem v1.0 - Unable to generate the SMPTE UHD-SDI RX Subsystem Example Design
(Xilinx Answer 71198) 2017.2-2017.4 Zynq UltraScale+ MPSoC VCU: PetaLinux fails to build gstreamer using sstate cache
(Xilinx Answer 70645) Zynq UltraScale+ MPSoC - Video Codec Unit (VCU)What video formats are supported in GStreamer?
(Xilinx Answer 70445) 2017.4 Vivado HLS - Windows OSMissing ports in the generated RTL when using hls::stream interfaces
(Xilinx Answer 66525) 2018.1 LogiCORE H.264/H.265 Video Codec Unit (VCU) v1.1Patch Updates for the LogiCORE H.264/H.265 Video Codec Unit (VCU) v1.1
(Xilinx Answer 69002) LogiCORE Video Frame Buffer Write v2.0 (Rev. 1) - Why does the Video Frame Write sometimes issue a write request to the AXI-MM interface even when there is no data to write?
(Xilinx Answer 64855) 2017.4 LogiCORE H.264/H.265 Video Codec Unit (VCU) v1.0 - Patch Updates for the LogiCORE H.264/H.265 Video Codec Unit (VCU) v1.0
(Xilinx Answer 70593) 2017.4 SMPTE UHD-SDI RX Subsystem v1.0 (Rev. 1) - Patch Updates for the SMPTE UHD-SDI RX Subsystem v1.0 (Rev. 1)
(Xilinx Answer 54546) HDMI Receiver (RX) Subsystem - Release Notes and Known Issues for the Vivado 2015.1 tool and later versions
(Xilinx Answer 65911) HDMI Transmitter (TX) Subsystem - Release Notes and Known Issues for the Vivado 2015.4 tool and later versions

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AR# 68819
Date 02/20/2019
Status Active
Type General Article
Boards & Kits
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