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  3. AR# 68866: Zynq UltraScale+ MPSoC - SGMII using PS-GTR - Why is the Zynq MP PHY driver reconfiguring the lanes previously set up for SGMII by the FSBL?

AR# 68866

Zynq UltraScale+ MPSoC - SGMII using PS-GTR - Why is the Zynq MP PHY driver reconfiguring the lanes previously set up for SGMII by the FSBL?

Description

Why is the Zynq MP PHY driver reconfiguring the lanes previously set up for SGMII by the FSBL?

Solution

The SERDES driver does not initialize the SGMII GT lane.

This issue is seen as a result of a work-around provided for silicon v1.0, but not applicable for 2.0.

To work-around the issue for v1.0 silicon, the xlnx,tx_termination_fix device-tree property should be removed from the device-tree. 

This will not reconfigure the PS GTR lanes.

AR# 68866
Date 05/08/2017
Status Active
Type General Article
Devices