The ADCCLK is derived from the DCLK using the clock divider in the XADC configuration register 0x42.
The DCLK and Clock divider setting must give an ADCCLK in the range of 1Mhz - 26Mhz.
In the XADC, if you set the clock divider to a value that gives an ADCLK frequency of less than 1Mhz then you can see the DRP port become unavailable.
In this example, DCLK is 100Mhz, and the clock divide value is 20, giving an ADCCLK frequency of 5MHz.
If I read Config2 from the DRP I observe that the CD bits are set to 0x14 (20)
If I now write 0xA5(165) to the CD bits in config2, the ADCCLK is set to be about 600Khz.
I now observe that JTAGLOCKED is stuck high.
No more reads or writes are possible over the DRP.
A read of config1 (0x41) should give 0x21ff on the DOUT bus.
The only way to recover from this is to rewrite a valid setting for the clock divider over JTAG.
set_property CONFIG_REG.CD 00010100 [get_hw_sysmons xilinx_tcf/Xilinx/0000100c27ba01/xc7k325t_0/SYSMON]
commit_hw_sysmon [get_hw_sysmons /xilinx_tcf/Xilinx/0000100c27ba01/xc7k325t_0/SYSMON]
In conclusion, writing settings to the clock divider that produce invalid ADCCLK clock frequencies should be avoided.