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AR# 68937

UltraScale/UltraScale+ DDR3 and DDR4 Memory IP Interface Calibration and Hardware Debug Guide

Description

The purpose of this Answer Record is to direct users to the appropriate information for debugging calibration and hardware failures on DDR3 or DDR4 memory interfaces generated by the programmable logic in UltraScale and UltraScale+ designs.

If a calibration failure occurs you will see the following message in the Vivado Tcl console:

WARNING: [Labtools 27-3410] Calibration Failed.
Resolution: For further debugging information, please refer to the Debug Guide that can be found from the following URL - https://www.xilinx.com/support/answers/68937.html

Solution

Documentation and Design Resources

UltraScale Architecture-Based FPGAs Memory IP Product Guide

  • (PG150) contains the design and debug information for all supported external memory types on UltraScale and UltraScale+ devices
    • The latest release is Version 1.4 published 06/07/2017

UltraScale Architecture PCB Design User Guide

  • (UG583) contains the UltraScale and UltraScale+ PCBA layout and routing requirements for all the supported external memory types and configurations
    • The latest release is Version 1.10 published 1/30/2017


Dumping XSDB Information through the Vivado Hardware Manager

Most of the critical information for debugging memory interface calibration and hardware failures is obtained through the XSDB logs. 

All of this information is available in the debugging section of (PG150).

Directions for Tcl Command Line:

get_hw_migs
  • This lists all of the memory interface cores in the design
report_property [lindex [get_hw_migs] x]
  • This dumps the XSDB information for the memory interface core specified by a number in the 'x' character position
  • Copy the response and save it to a separate file

  • In cases where you want to refresh the XDSB properties after the memory interface core has been running or has been unexpectedly reset, use the refresh command:
refresh_hw_mig [lindex [get_hw_migs] x]
  • Note: For single memory interface core designs, the core designation in the examples above will be 0.


Directions for Vivado Hardware Manager GUI:

  • Launch the Vivado Hardware Manager and connect to the device
  • Select the MIG core in the Hardware window
    • The Status column in this window indicates if the MIG core passed or failed calibration
  • When the MIG core is selected right click and select Open Dashboard from the context menu




  • Below the Hardware window will be the MIG Core Properties window
    • Go to the Properties tab, right click anywhere in the field, and select the Export to Spreadsheet option in the context menu




  • Select the location and name of the file to save, use all the default options, and then select OK to save the file
    • The file should be a few thousand lines long depending on the width of the memory interface




  • In the MIG Dashboard window note the Properties and Status windows
    • These windows have the general information about the status of the MIG core such as if it passed calibration or if it failed, and then in what stage




  • Take a screenshot of this information and use it for a reference
  • On the right side of the MIG Dashboard is the Calibration/Margins window




  • Select the 'Chart - Center Aligned' tab at the bottom of the window
  • Take screenshots of the Read and Write modes for both Simple and Complex (if applicable) patterns as well as the Rising and Falling Clock Edges
    • This information gives a visual representation of the window margin size







DDR3/DDR4 Calibration and Hardware Debugging

When there is a calibration failure or hardware issue with a DDR3/DDR4 interface follow these instructions to debug the design:

  • Download the latest version of (PG150) and (UG583)
  • In the case of a calibration failure, note the failing stage and error message reported in the Vivado Hardware Manager for that memory interface core
  • Open (PG150) and go to the section called Hardware Debug in Section IX Debugging and read through the General Checks section
  • Double check the PCB Guidelines for Memory Interfaces in (UG583)
  • Go to the Debugging DDR3/DDR4 Designs section of (PG150) and read through the Calibration Stages and Determine the Failing Calibration Stage sections
  • Once you have determined the failing calibration stage go to (Xilinx Answer 62181) and download the Hardware Debug Best Practices document
    • A good first step to debugging calibration issues is to make power supply measurements as described in Chapter 1: Power Supplies for all DRAM, FPGA core, and I/O related voltage rails as well as the local ground planes
    • Based on the recommendations from debugging the failing calibration stage in (PG150), be prepared to take signal integrity measurements as described in Chapter 2: Signal Integrity on Critical Nets

Using the DDR3/DDR4 Example Design for Calibration Debug

  • Another useful tool for debugging DDR3/DDR4 calibration failures is to generate the IP example design
    • The IP example design is a quick and easy way to generate a DDR3/DDR4 design with little effort from the end user but it provides a clean sandbox in order to accelerate debugging
  • To generate the IP example design select your target FPGA, add the IP, and configure it to match your current clocking and memory topology
  • In the "Advanced Options" tab enable the debug signals for the controller and select either the Simple TG or the Advanced TG (Advanced TG is not available for AXI designs)
  • Once complete select "OK" and when prompted select the "Global" synthesis option
  • After this go to the Sources window and in the Hierarchy tab right click on the DDR3/DDR4 *.xci file and select the "Open IP Example Design" option
    • This will launch a new Vivado session
    • You will see that the DDR3/DDR4 core is generated with the traffic generator and all of the necessary ILA and VIO debug signals described in (PG150) to debug calibration issues
  • From here you can add your existing XDC file and then go through the flow to generate a bitstream
    • Make sure to double check the clock assignments and reset polarities to match the rest of the design
  • Now you can quickly made a fully instrumented DDR3/DDR4 design with a traffic generator that will hopefully make debugging the design much easier
  • Knowing how to make the IP example design will also make it easier to isolate board issues either by generating narrower memory interfaces that only affect the failing byte lane. Alternatively, you can exercise the memory interface with stressful patterns using the ATG
  • Another quick check is to decrease the memory interface frequency to see if it passes calibration or if the design can make it further in the calibration process


Revision History
08/17/2017 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 68937
Date 11/08/2017
Status Active
Type Error Message
Devices
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
Tools
  • Vivado Design Suite
IP
  • DDR3 SDRAM
  • DDR4 SDRAM
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