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AR# 68938

Soft Error Mitigation (SEM) IP – UltraScale+ Architecture SSI VU13P [Timing 38-282] Negative SETUP slack violation

Description

The VU13P Soft Error Mitigation (SEM) IP does not meet timing with the maximum supported frequency of 125MHz (8000 ps).


An example path is given below:

Max Delay Paths

>--------------------------------------------------------------------------------------

> Slack (VIOLATED) :        -0.442ns  (required time - arrival time)

>   Source:                example_support_wrapper/example_support/example_cfg/slr3_cfg_frame_ecce4/ICAPTOPCLK

>                             (rising edge-triggered cell FRAME_ECCE4 clocked by clk  {rise@0.000ns fall@4.000ns period=8.000ns})

>   Destination:            example_support_wrapper/example_support/sem_controller/inst/controller/slr3_fecc_endofframe_reg1_reg/D

>                             (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@4.000ns period=8.000ns})

>   Path Group:             clk

>   Path Type:              Setup (Max at Slow Process Corner)

>   Requirement:            8.000ns  (clk rise@8.000ns - clk rise@0.000ns)

>   Data Path Delay:        8.215ns  (logic 2.430ns (29.580%)  route 5.785ns (70.420%))

>   Logic Levels:           0 

>   Clock Path Skew:        0.138ns (DCD - SCD + CPR)

>     Destination Clock Delay (DCD):    4.106ns = ( 12.106 - 8.000 )

>     Source Clock Delay      (SCD):    4.393ns

>     Clock Pessimism Removal (CPR):    0.425ns

>   Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE

>     Total System Jitter     (TSJ):    0.071ns

>     Total Input Jitter      (TIJ):    0.000ns

>     Discrete Jitter          (DJ):    0.000ns

>     Phase Error              (PE):    0.000ns

>   Inter-SLR Compensation: 0.357ns  ((DCD - CCD) * PF)

>     Destination Clock Delay (DCD):    4.106ns

>     Common Clock Delay      (CCD):    1.727ns

>     Prorating Factor         (PF):    0.150

>   Clock Net Delay (Source):      3.586ns (routing 1.289ns, distribution 2.297ns)

>   Clock Net Delay (Destination): 3.607ns (routing 1.177ns, distribution 2.430ns) 

Solution

This timing issue can be resolved by removing the 1st register stage that registers the output of FRAME_ECC4 in SLR3 from the controller pblock.

The constraint is provided below:

remove_cells_from_pblock sem [get_cells example_support_wrapper/example_support/sem_controller/inst/controller/slr3_fecc_*_reg1*]

After adding the above constraint, the design meets timing, but it creates a Critical Warning and Warning. 

Because the constraint is properly applied in implementation, these warnings can be safely ignored.

The Critical Warning and Warning message are provided below:

CRITICAL WARNING: [Vivado 12-1039] No cells specified to remove.

WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [ ] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [] and check the run log file to verify that these constraints were correctly applied.

This issue will be addressed in a future release.

AR# 68938
Date 04/19/2017
Status Active
Type General Article
Devices
  • Virtex UltraScale+
Tools
  • Vivado Design Suite - 2017.1
IP
  • Soft Error Mitigation
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