The VU13P Soft Error Mitigation (SEM) IP does not meet timing with the maximum supported frequency of 125MHz (8000 ps).
An example path is given below:
This timing issue can be resolved by removing the 1st register stage that registers the output of FRAME_ECC4 in SLR3 from the controller pblock.
The constraint is provided below:
After adding the above constraint, the design meets timing, but it creates a Critical Warning and Warning.
Because the constraint is properly applied in implementation, these warnings can be safely ignored.
The Critical Warning and Warning message are provided below:
This issue will be addressed in a future release.