AR# 68962

How can I get a Zynq MPSoC PS pl_resetnx port's control address?

Description

Unlike Zynq 7000, where the information can be found in (UG585), it is not straightforward to get the address information of PL resets in Zynq MPSoC.

If I wish to trigger the reset for pl_resetn0 for example, how do I get the correct address to control it?

Solution

The PL resetn0 is mapped to EMIO 95.


This can be seen in Zynq MPSoC PCW when no IP and resets are selected.

At this time, all of the EMIO will be available, for example GPIO EMIO [95:0]:

 




 

 

When you select a PL reset, in this case pl_reset0 as shown below then the EMIO 95 will be routed to pl_reset0.

 




 

As a result only the EMIO [94:0] pin will be available.

 





 

Similarly, EMIO 94 is for pl_reset1, EMIO 93 is for pl_reset2 and EMIO 92 is for pl_reset3.

 

 

To obtain the register details (bolded below) of pl_reset0, check the psu_ps_pl_reset_config_data() function inside the psu_init.c file.

 

unsigned long psu_ps_pl_reset_config_data() {

                              // : PS PL RESET SEQUENCE

                              // : FABRIC RESET USING EMIO

                              /*Register : MASK_DATA_5_MSW @ 0XFF0A002C</p>

 

                              Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]

                              PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW                                             0x8000

 

                              Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)

                              (OFFSET, MASK, VALUE)      (0XFF0A002C, 0xFFFF0000U ,0x80000000U) 

                              RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK |  0 );

 

                              RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT

                                             |  0 ) & RegMask); */

                              PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U);

               /*###############################################################
############################################################# */

 

                              /*Register : DIRM_5 @ 0XFF0A0344</p>

 

                              Operation is the same as DIRM_0[DIRECTION_0]

                              PSU_GPIO_DIRM_5_DIRECTION_5                                                     0x80000000

 

                              Direction mode (GPIO Bank5, EMIO)

                              (OFFSET, MASK, VALUE)      (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) 

                              RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK |  0 );

 

                              RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT

                                             |  0 ) & RegMask); */

                              PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);

               /*###############################################################
############################################################# */

 

                              /*Register : OEN_5 @ 0XFF0A0348</p>

 

                              Operation is the same as OEN_0[OP_ENABLE_0]

                              PSU_GPIO_OEN_5_OP_ENABLE_5                                                      0x80000000

 

                              Output enable (GPIO Bank5, EMIO)

                              (OFFSET, MASK, VALUE)      (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) 

                              RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK |  0 );

 

                              RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT

                                             |  0 ) & RegMask); */

                              PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);

               /*###############################################################
############################################################# */

 

                              /*Register : DATA_5 @ 0XFF0A0054</p>

 

                              Output Data

                              PSU_GPIO_DATA_5_DATA_5                                                          0x80000000

 

                              Output Data (GPIO Bank5, EMIO)

                              (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) 

                              RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );

 

                              RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT

                                             |  0 ) & RegMask); */

                              PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);

               /*##############################################################
############################################################## */

 

                              mask_delay(1);

 

               /*#############################################################
############################################################### */

 

                              // : FABRIC RESET USING DATA_5 TOGGLE

                              /*Register : DATA_5 @ 0XFF0A0054</p>

 

                              Output Data

                              PSU_GPIO_DATA_5_DATA_5                                                          0X00000000

 

                              Output Data (GPIO Bank5, EMIO)

                              (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) 

                              RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );

 

                              RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT

                                             |  0 ) & RegMask); */

                              PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U);

               /*##############################################################
############################################################## */

 

                              mask_delay(1);

 

               /*##############################################################
############################################################## */

 

                              // : FABRIC RESET USING DATA_5 TOGGLE

                              /*Register : DATA_5 @ 0XFF0A0054</p>

 

                              Output Data

                              PSU_GPIO_DATA_5_DATA_5                                                          0x80000000

 

                              Output Data (GPIO Bank5, EMIO)

                              (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) 

                              RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );

 

                              RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT

                                             |  0 ) & RegMask); */

                              PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);

               /*##############################################################
############################################################## */

 

 

  return 1;

}

 

 

AR# 68962
Date 08/11/2017
Status Active
Type General Article
Devices
Tools
IP
Boards & Kits