AR# 6901

SYNPLIFY: The GR pin is not listed in the EDIF netlist when targetting the XC5200

Description

Keywords: gr, 5200, EDIF, Verilog, Synplify

Urgency: Hot

General Description:
In a XC5200 family design with asynchronous resets
flip-flops and an instantiated STARTUP cell, the GR pin
is not listed in the EDIF netlist.

Solution

Change the output format from EDIF to XNF.
AR# 6901
Date 10/03/2008
Status Archive
Type General Article