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SYNPLIFY: The GR pin is not listed in the EDIF netlist when targetting the XC5200
Keywords: gr, 5200, EDIF, Verilog, Synplify
In a XC5200 family design with asynchronous resets
flip-flops and an instantiated STARTUP cell, the GR pin
is not listed in the EDIF netlist.
Change the output format from EDIF to XNF.
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