UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6901

SYNPLIFY: The GR pin is not listed in the EDIF netlist when targetting the XC5200

Description

Keywords: gr, 5200, EDIF, Verilog, Synplify

Urgency: Hot

General Description:
In a XC5200 family design with asynchronous resets
flip-flops and an instantiated STARTUP cell, the GR pin
is not listed in the EDIF netlist.

Solution

Change the output format from EDIF to XNF.
AR# 6901
Date Created 08/21/2007
Last Updated 10/03/2008
Status Archive
Type General Article