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AR# 69021

JESD204 - 2017.1 - UltraScale / UltraScale+ IBUFDS_GTE output instability


When using the JESD204 core and PHY with clock configuration using the refclk as the core clock, clock output instability from the IBUFDS_GTE might be seen.



The IBUFDS_GTE which feeds the core_clk cannot be guaranteed to be stable until 250 us after the device configuration completes.

For this reason, the core and anything that is clocked by core_clk (for example, any AXI4-Stream logic) must be kept in reset for 250 us after device configuration completes.

AR# 69021
Date 04/19/2017
Status Active
Type General Article
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