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AR# 69023

2017.x Vivado Synthesis - Known Issues


This answer record lists known issues for 2017.x Vivado Synthesis.


2017.1 Vivado Synthesis Known Issues

(Xilinx Answer 64777)Vivado Synthesis - SystemVerilog case inside range expression support
(Xilinx Answer 67947)Vivado Synthesis - XDC read in before a second synth_design run is not use by Synthesis in non-project mode TCL script flow
(Xilinx Answer 66280)Vivado Synthesis - Port logic trimmed when System Verilog interface contains no port direction
(Xilinx Answer 67946)Vivado Synthesis - Using VHDL configuration without the component instantiation statement is not supported
(Xilinx Answer 67943)Vivado Synthesis - "black_box = false" does not work
(Xilinx Answer 66484) Vivado Synthesis - Using incorrect mem files with readmemh in Synthesis
(Xilinx Answer 65764)Vivado Synthesis - Parameterized Instantiation is not supported for bottom-up OOC flow
(Xilinx Answer 66918)Vivado Synthesis - Partial assignments to generic arrays in component map is not handled correctly
(Xilinx Answer 66920)Vivado Synthesis - Port defined as a record that contains a null vector gets entire record/port ignored
(Xilinx Answer 65418)Vivado Synthesis - Verilog port direction problem in RTL not messaged by Vivado
(Xilinx Answer 65407)2014.3 Synthesis - Error [Synth 8-1730] cannot call side-effect procedure print from within pure function XX
(Xilinx Answer 65409)Vivado Synthesis - "[Synth 8-658] type mismatch for port" Port mapping with VHDL alias results in Vivado Synthesis error
(Xilinx Answer 65413)Vivado Synthesis: RLOC and BEL attributes not supported when accessing array of strings
(Xilinx Answer 65419)Vivado Synthesis - Long Runtime for RAM Initialization Code
(Xilinx Answer 64019)Vivado Synthesis - ASYNC_REG is not getting applied to the registers when applied on net signals in HDL
(Xilinx Answer 64023)Vivado Synthesis - Hierarchical name used in defparam causes "ERROR: [Synth 8-27] complex defparam not supported"
(Xilinx Answer 64021)Vivado Synthesis - RAM not inferred when "wait until" is used for clock
(Xilinx Answer 63992)Vivado Synthesis - The LUT1 inverter in the feedback loop of the register also gets replicated when Synthesis replicates the register due to MAX_FANOUT attribute
(Xilinx Answer 64042)Vivado Synthesis - Using 'X' and 'U' comparison in VHDL results in unexpected logic in Synthesized netlist
(Xilinx Answer 64032)Vivado Synthesis - CRITICAL WARNING: [Netlist 29-180] Cell 'FDCPE' is not a supported primitive for virtexu part
(Xilinx Answer 64031)Vivado Synthesis - Issues using custom attribute in RTL
(Xilinx Answer 64030)Vivado Synthesis - MAX_FANOUT applied on only one bit of a wide bus in XDC gets annotated to the other bits
(Xilinx Answer 64049)Vivado Synthesis - Register is not absorbed into BRAM when its reset value or initial value is non-zero
(Xilinx Answer 64034)Vivado Synthesis - Getting "ERROR: [Synth 8-659] type mismatch in port association" when running OOC flow where the netlist tool cannot put the top level and OOC modules together
(Xilinx Answer 64033)2015.1 Vivado Synthesis: ERROR: [Synth 8-5548] Non zero range declaration for RAM (mem_reg) not supported. Use 0 for MSB or LSB for RAM declaration
(Xilinx Answer 64044)Vivado Synthesis - WARNING: [Synth 8-152] case item 2'bx1 overlaps with previous case item(s)
(Xilinx Answer 62162)Vivado Synthesis - Why does MAX_FANOUT not work when the load is in a different hierarchy and hierarchy is preserved ?
(Xilinx Answer 62099)Vivado Synthesis - Why do flip-flops not get packed into the IOB when DONT_TOUCH & IOB attributes are applied in HDL?
(Xilinx Answer 58025)Vivado Synthesis - BRAM inference fails due to the synchronous reset on the Synchronous read address register
(Xilinx Answer 61922)Vivado Synthesis - Does Vivado Synthesis make use of the parity bits for Asymmetric BRAM inference?
(Xilinx Answer 62165)Vivado Synthesis - ERROR: [Synth-1716] cannot access 'i' from inside pure function 'foo'.
(Xilinx Answer 62121)Vivado Synthesis - Non-integer generics are not supported in TCL/GUI mode
(Xilinx Answer 61995)Vivado Synthesis - Sub-optimal inference of Block-RAM (bad area QoR) when the depth is non-power of 2
(Xilinx Answer 60921)Vivado Synthesis - FIFO_SYNC_MACRO is trimmed by synthesis
(Xilinx Answer 60912)Vivado Synthesis: Verilog parameter overridden within instantiation fails with "ERROR:[Synth 8-3438]"
(Xilinx Answer 60913)2014.2 Vivado Synthesis does not infer DSP48 for constant multiplier by default
(Xilinx Answer 61009)2014.x Vivado Synthesis - MREG is always be chosen over PREG if only one of them can be used when inferring DSP48
(Xilinx Answer 60104)Vivado Synthesis - FSM is not inferred where state register is assigned with a signal (non-constant)
(Xilinx Answer 61027)Vivado Synthesis - The "Block RAM" Table in Synthesis report doesn't reflect all BRAMs used in design
(Xilinx Answer 61030)Vivado Synthesis - "ERROR: [Synth 8-26]" is given when SystemVerilog file with a struct type instantiates VHDL with a port of record type
(Xilinx Answer 57854)2014.1 Vivado Synthesis - Some patterns of asymmetric BRAM inference are not successful
(Xilinx Answer 60057)2014.1 Vivado Synthesis - "IO_BUFFER_TYPE" attribute set to "IBUFG" on input port does not work
(Xilinx Answer 60061)Vivado Synthesis - INIT value of Inferred dynamic SRL is not correct
(Xilinx Answer 60054)Vivado Synthesis - "ERROR: [Synth 8-517]" is given when '0' and 'L' or '1' and 'H' values are both used in case statement
(Xilinx Answer 60092)Vivado Synthesis - Submodule interface gets modified even with "-flatten_hierarchy none" when there are tricells in the lower level hierarchy
(Xilinx Answer 60073)2014.1 Vivado Synthesis - ERROR: [Synth 8-3380] loop condition does not converge after 2000 iterations
(Xilinx Answer 60015)2014.1 Vivado Synthesis - ERROR: [Synth 8-550] port width mismatch in instance array for port 'din[a]'
(Xilinx Answer 60013)Vivado Synthesis - "Critical Warning : [Synth 8-3352] multi-driven net" caused by continuous assign statements along with wire declaration
(Xilinx Answer 60011)Vivado Synthesis log files in project mode vs non-project mode.
(Xilinx Answer 59980)Vivado Synthesis - When moving from 2013.4 to 2014.1, getting a message that says "Vivado no longer uses 'work' as the default library. Your files have been moved to a new default library 'xil_defaultlib'"  
(Xilinx Answer 60213)Vivado Synthesis - LOC constraint applied in RTL on ports that are vectors is not supported
(Xilinx Answer 58574)2013.3 Vivado-Synthesis: Is there any limit on the minimum number of states required to infer FSM?
(Xilinx Answer 57981)Vivado Synthesis - Do we pack ROM into block RAM when there is an incompatible interface on the input side?
(Xilinx Answer 58691)Vivado Synthesis - A CRITICAL WARNING occurs stating that an existing primary or secondary unit is being overwritten [Synth 8-4527] or [Synth 8-4528]
(Xilinx Answer 57983)Vivado synthesis - Loose timing constraints results in LUTRAM instead of block RAM
(Xilinx Answer 57963)Vivado Synthesis - Unconnected pins on BlackBox.
(Xilinx Answer 57975)Vivado Synthesis - Issue with array of instances when using SystemVerilog unpacked arrays
(Xilinx Answer 57984)Does Vivado Synthesis support $clog2 function?
(Xilinx Answer 56211)Does Vivado Synthesis support two dimensional array initialization using reg declaration?
(Xilinx Answer 57964)Vivado Synthesis - Issue with VHDL Time data Type
(Xilinx Answer 58022)Vivado Synthesis - Netlist names for signals coming from VHDL record types have changed.
(Xilinx Answer 56456)Vivado Synthesis - How to manually setup my HDL files?
(Xilinx Answer 56457)Vivado Synthesis - Does Vivado Synthesis infer an optimal block RAM when both read address and the output data are registered in the HDL code?
(Xilinx Answer 55914)Vivado Synthesis - What is Vivado Synthesis include file search order for project, non-project modes?
(Xilinx Answer 54074)Vivado Synthesis - Synthesis give a "Module not found" error for an EDIF module.
(Xilinx Answer 55989)Vivado Synthesis - Why will a Xilinx IP not get flattened completely?
(Xilinx Answer 56371)Vivado Synthesis - How do you speed up XDC constraints processing during synthesis?
(Xilinx Answer 56370)Vivado Synthesis - "-verbose" switch of synth_design Tcl command does not work correctly and what would be the alternate option?
(Xilinx Answer 55942)Vivado - Vivado Synthesis - Why are the inputs to my EDIF/NGC files left unconnected?
(Xilinx Answer 55203)Vivado - 2013.x Vivado Synthesis - What is the purpose of RuntimeOptimized option when passed to -directive switch?
(Xilinx Answer 55224)Vivado - 2013.x Vivado Synthesis - What is the purpose of "out_of_context" option used as part of the -mode switch?
(Xilinx Answer 55225)Vivado - Vivado Synthesis - How to get around longer constraint validation time during early development cycles?
(Xilinx Answer 51163)Vivado Synthesis - MAX_FANOUT Synthesis Attribute not supported for edif netlist files
(Xilinx Answer 55302)Vivado Synthesis - Alternative HDL coding style to reduce longer runtimes.
(Xilinx Answer 55135)Vivado Synthesis - Unsupported System Verilog constructs
(Xilinx Answer 55196)Vivado Synthesis - What features are not supported by Vivado Synthesis for DSP48 inference?
(Xilinx Answer 55194)Vivado Synthesis - What are Vivado Synthesis best practices for System Verilog?
(Xilinx Answer 54551)Vivado Synthesis - How does Vivado Synthesis treat imported core netlists today?
(Xilinx Answer 53524)Vivado Synthesis - Does Vivado Synthesis merge multiple registers that are declared separately and used as the output register bus of a DSP48?
(Xilinx Answer 53505)Vivado 2012.x - Vivado Synthesis - Does Vivado Synthesis infer a block RAM on an asynchronous reset output register?
(Xilinx Answer 53507)Vivado 2012.x - Vivado Synthesis - Does Vivado Synthesis infer block RAM for multi-dimensional arrays greater than two dimensions?
(Xilinx Answer 52335)What are the recommended steps to be followed today in order to do bottom-up synthesis using the Vivado Synthesis tool?
(Xilinx Answer 52333)Why does Vivado Synthesis generate "ERROR: [Synth 8-2914] Unsupported RAM template" when more than two clocks are present within a block RAM memory inferring HDL code?
(Xilinx Answer 52331)Does Vivado Synthesis support VHDL record type to model a memory and infer a block RAM?
(Xilinx Answer 52304)Does Vivado Synthesis support IEEE MATH_REAL and PROPOSED package libraries?
(Xilinx Answer 52303)Does Vivado Synthesis support resettable memory array?
(Xilinx Answer 52301)Does Vivado Synthesis support the READ_CORES option?
(Xilinx Answer 46743)Would Vivado Synthesis be able to infer 3-state logic in a lower level design when flatten_hierarchy is set to none?
(Xilinx Answer 52086)Vivado Synthesis - WARNING: [Synth 8-1824] circular dependency found for file <name>.vhd while ordering
(Xilinx Answer 47454)Vivado Synthesis - Does Vivado synthesis support Verilog Module instantiation in VHDL entity via work library?
(Xilinx Answer 51087)Does Vivado Synthesis tool support physical constraints?
(Xilinx Answer 51088)As part of True Dual Port RAM coding styles, does Vivado Synthesis generate RAMs when both ports are specified in the same always/process block?

2017.1 Vivado Synthesis Resolved Issues

(Xilinx Answer 67948)Vivado Synthesis - Post-Synthesis DRC Warning PLHOLDVIO #1: A LUT <LUT_cell_name> is driving clock pin of n cells

AR# 69023
Date 04/19/2017
Status Active
Type General Article
  • Vivado Design Suite
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