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AR# 69027

JESD204 - Single Lane JESD204 Transmit Example Design simulations timing out when using QuestaSim

Description

When running a JESD204 Single Lane Transmit configuration example design using QuestaSim, a simulation time-out might occur.  

 

Solution

This time-out scenario can be prevented by updating the Elaboration settings in Vivado Design Suite before launching the simulation.

In the Project Settings, under the Elaboration tab, add the '-noprotectopt' switch under more options.

 

g

 

This ensures that the switch is added to the elaborate.do file and the simulation will run without timing out.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
65479 JESD204B - Single Lane JESD204 Transmit Example Design Simulations Timing Out When Using QuestaSim N/A N/A
AR# 69027
Date 04/26/2017
Status Active
Type General Article
IP
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