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AR# 69035

DDR4 UltraScale and UltraScale+ IP Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the DDR4 UltraScale and UltraScale+ Cores and includes the following:

  • Supported Devices
  • General Information
  • Known Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

MIG IP Page:



General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

DDR4 VersionVivado Tools Version
v2.2 (Rev. 1)2017.2
v2.1 (Rev. 1)2016.4
v2.0 Rev12016.2
v5.0 Rev12014.2

* Starting with the release of Vivado 2015.3, the MIG wizard is no longer used. A separate wizard exists for all supported memory interface types. Therefore, the core versions reset to 1.0.

For a list of supported memory interfaces and features for UltraScale FPGAs, see the LogiCORE IP UltraScale Architecture-Based FPGAs Memory Interface Solutions Product Guide (PG150) located at:


For a complete list of supported memory devices please refer to the attached spreadsheet called "memory_device_support_ddr4.xlsx".

For a list of supported frequencies for UltraScale FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the UltraScale Documentation Center.

For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

The MIG tool includes the appropriate frequency range for each specific memory interface configuration

Table 2 provides answer records for general guidance when using the MIG UltraScale core.

Table 2: General Guidance

Answer RecordTitle
(Xilinx Answer 59625)MIG UltraScale - Design Methodology Checklist
(Xilinx Answer 61304)MIG UltraScale - Clocking Guidelines and Requirements
(PG150) - DebuggingMIG UltraScale DDR4/DDR3 - Hardware Debug Guide
(Xilinx Answer 63462)MIG UltraScale - Sample CSV data file for creating Custom Parts
(Xilinx Answer 63831)MIG UltraScale - Migrating and Upgrading IP into 2015.1
(Xilinx Answer 61598)Design Advisory Master Answer Record for Kintex UltraScale FPGA
(Xilinx Answer 61930)Design Advisory Master Answer Record for Virtex UltraScale FPGA
(Xilinx Answer 62483)Design Advisory for MIG UltraScale (all memory types) - VRP pin and DCI Cascade requirements
(Xilinx Answer 68169)Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs

Known and Resolved Issues

The following table provides known issues for the MIG UltraScale core, starting with v5.0, initially released in the Vivado 2014.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


The following table provides known issues for MIG UltraScale DDR4.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 69291)UltraScale+ Memory IP - The SFVA625 package does not support PL Memory Interfacesv2.2v2.2 (Rev. 1)
(Xilinx Answer 67956)DDR4/DDR3 UltraScale IP - Supported configurations for Self Refresh and Save/Restorev2.1v2.2 (Rev. 1)
(Xilinx Answer 67979)DDR4 UltraScale IP - Design generation error occurs due to incorrect maximum MMCM VCO value for -1H speed gradev2.1NAB
(Xilinx Answer 66471)DDR4 IP - Incorrect Write Recovery (WR) value programmed to Mode Register 0 (MR0)v1.1Not Resolved
(Xilinx Answer 68236)DDR4 IP - upgrading locked IP may fail for select RDIMMsv2.1 (Rev. 1)v2.2
(Xilinx Answer 67392)
UltraScale and UltraScale+ Memory IP - pulse width violations can occur
v2.0 (Rev 1)
(Xilinx Answer 67967)UltraScale Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency rangev2.1v2.1 (Rev. 1)
(Xilinx Answer 67957)UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IPv2.1v2.1 (Rev. 1)
(Xilinx Answer 67933)UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.v2.1v2.1 (Rev. 1)
(Xilinx Answer 68143)DDR4 IP - IP GUI hangs and crashes for specific settingsv2.1v2.1 (Rev 1)
(Xilinx Answer 68028)UltraScale Memory IP - Pulse width violations occur for designs that violate the maximum BUFGCE timing spec with the Reference Input Clock Speed (ps)v2.1v2.2
(Xilinx Answer 67230)UltraScale DDR4 SDRAM IP - tREFI interval is incorrectly setv2.0v2.1 (Rev 1)
(Xilinx Answer 67891)DDR4/DDR3 IP - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation modev2.0 (Rev. 1)v2.1
(Xilinx Answer 67684)UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problemsv2.0 (Rev. 1)v2.1
(Xilinx Answer 67631)UltraScale DDR4 IP - some parts use the incorrect memory speed gradev2.0 (Rev. 1)v2.1
(Xilinx Answer 67455)UltraScale DDR3 and DDR4 IP - ECC signals are missing from the User Interface when ECC is enabled without AXIv2.0 (Rev. 1)v2.1
(Xilinx Answer 67335)UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skippedv2.0 (Rev. 1)v2.1
(Xilinx Answer 66951)Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term checkv2.0v2.1
(Xilinx Answer 67255)UltraScale and UltraScale+ DDR4 SDRAM IP - [Place 30-487] error may occur for some configurationsv2.0v2.1
(Xilinx Answer 67008)DDR4 UltraScale - Enabling DBI Read causes Read Complex register values in XSDB BRAM to not be populatedv2.0v2.1
(Xilinx Answer 66951)Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term checkv2.0v2.1
(Xilinx Answer 66938)DDR4 UltraScale+ - Usage of six or more DDP (Dual Die Package/Twin Die) components is limited to 2133Mbps operation. This limit is not adhered to within the DDR4 Wizard. Manual adherence to this limit requiredv2.0v2.1
(Xilinx Answer 66360)UltraScale Memory IP - Core Container does not include *.csv file when a custom memory part is createdv1.1v2.1
(Xilinx Answer 67544)DDR4/DDR3 UltraScale IP - Data errors seen at user interface when using Normal Ordering Error. The errored data presented is correct data from a later read from the same address. App_rdy might get stuck low.Initial Releasev2.1
(Xilinx Answer 67225)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IPv2.0v2.0 Rev1
(Xilinx Answer 67224)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCMv2.0v2.0 Rev1
(Xilinx Answer 67164)UltraScale+ Memory IP - timing failures occur due to high congestion levelsv2.0v2.0 Rev1
(Xilinx Answer 67054)DDR4 IP - Extra CK/CK# clock pair generated for 3DS RDIM part M393A8K40B21-CTCv2.0v2.0 Rev1
(Xilinx Answer 66937)DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore optionsv2.0v2.0 Rev1
(Xilinx Answer 66927)DDR4 and DDR3 IP - BFM simulations have errors when using Self Refresh and Self Restore optionsv2.0v2.0 Rev1
(Xilinx Answer 66678)UltraScale Memory IP - Design fails during 'opt_design' when using Custom CSVv1.1v2.0 Rev1
(Xilinx Answer 66554)DDR4 IP - a 300MHz reference input clock cannot be chosen for 1333MHz (750ps) output clock frequencyv1.1v2.0 Rev1
(Xilinx Answer 65083)DDR4/DDR3 SDRAM IP - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 packagev1.0v2.0 Rev1
(Xilinx Answer 64774)MIG UltraScale DDR4 - SETUP/HOLD violations in the mmcm_clkout0 domainv7.0v2.0
(Xilinx Answer 65950)MIG UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs might fail in calibrationv1.0v2.0
(Xilinx Answer 65372)DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulatorv1.0v2.0
(Xilinx Answer 64784)MIG UltraScale DDR4 - false DRC MIG-32# errors detected for sys_clk_p/nv7.0v2.0
(Xilinx Answer 62543)MIG UltraScale - Certain speed grades incorrectly prevent previously allowed input clock periodsv6.0v2.0
(Xilinx Answer 65327)UltraScale Memory IP - CRITICAL WARNING: [Xicom 50-38] xicom: The current version of Vivado does not support this detected version of the MIG core. 2015.2 is the last version supporting it.v1.0NA
(Xilinx Answer 64856)Design Advisory for UltraScale DDR4/DDR3 - PCB pull-down required on the DDR3 RESET# pin and on the DDR4 RESET_N pin to maintain logic low during memory initializationInitial Release
(Xilinx Answer 64778)MIG UltraScale - When using the Auto Assign feature of Bank Planner, an error message is not issued when the memory ports do not fit into a half bankv7.0v1.1
(Xilinx Answer 65431)UltraScale Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraintv1.0NA
(Xilinx Answer 65790)DDR4/DDR3 SDRAM IP - when using a Custom Memory part some timing parameters are not updated correctlyv1.0v1.1
(Xilinx Answer 65652)DDR3/DDR4 SDRAM IP - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Writev1.0v1.1
(Xilinx Answer 65493)DDR4/3 UltraScale - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banksv1.0v1.1
(Xilinx Answer 65370)Memory IP - pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory I/O is located inv1.0v1.1
(Xilinx Answer 64188)MIG UltraScale - sys_rst missing set_false_path constraintv7.0v1.1
(Xilinx Answer 63667)MIG UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Modelv7.0v1.1
(Xilinx Answer 62086)MIG UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mappingv5.0 Rev1v1.1
(Xilinx Answer 65261)MIG UltraScale DDR4/DDR3 - Dynamic DCI does not work for select devicesv7.1v1.0
(Xilinx Answer 65054)MIG UltraScale DDR4 - CAS Latency setting of 17 results in calibration failures during DQS Gate Calibrationv7.1v1.0
(Xilinx Answer 64923)MIG UltraScale - [Xicom 50-24] error message occurs after programing devicev7.0v1.0
(Xilinx Answer 64887)MIG UltraScale - Errors occur when implementing a 2015.1 MIG IP in Vivado 2015.2 - Patch availablev7.0v1.0
(Xilinx Answer 64773)MIG UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IPv7.0v1.0
(Xilinx Answer 64071)MIG UltraScale - custom memory parts fail simulationv7.0v1.0
(Xilinx Answer 64615)MIG UltraScale - AXI Interface Efficiency improvements for 2015.2v7.0v7.1
(Xilinx Answer 64306)MIG UltraScale DDR4 - Required calibration patch to resolve potential hardware failures due to incorrect DLL Reset during SDRAM initialization sequence (all configurations) and internal nibble clocking (x4 only)v7.0v7.1
(Xilinx Answer 64010)MIG UltraScale DDR4/DDR3 - memory controller may hang when in "Strict" modev7.0v7.1
(Xilinx Answer 64069)MIG UltraScale - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pinsv7.0v7.1
(Xilinx Answer 64063)MIG UltraScale DDR4/3 - DIMM tool tip incorrectly lists the density for the base component partv7.0v7.1
(Xilinx Answer 63786)MIG UltraScale - SPEC_VIOLATION tWR/tRTP tWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Modelv7.0v7.1
(Xilinx Answer 63666)MIG UltraScale DDR4 - tCK SPEC_VIOLATION for tCK = 833ps and speed bin = 833 when using Micron Memory Modelv7.0v7.1
(Xilinx Answer 64431)MIG UltraScale - ]Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 0.v6.1v7.0
(Xilinx Answer 63596)MIG UltraScale - HOLD violations may be seen when using 2014.4.1v6.1v7.0
(Xilinx Answer 64070)MIG UltraScale - designs with multiple controllers may generate ERROR::34 messagev6.1v7.0
(Xilinx Answer 63261)MIG UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during Lint checkv6.1v7.0
(Xilinx Answer 63240)MIG UltraScale DDR4/DDR3 - PHY Only Documentation - PG150 includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation)v6.1v7.0
(Xilinx Answer 62930)MIG UltraScale DDR3/DDR4 - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurationsv6.1v7.0
(Xilinx Answer 63022)MIG UltraScale DDR4/3 - Designs targeting dual rank DIMMs with address mirroring fail in hardwarev6.0v7.0
(Xilinx Answer 62776)MIG UltraScale DDR3/DDR4 - ECC fault injection does not workv6.1v7.0
(Xilinx Answer 62774)MIG UltraScale - timing failures may be seen with MIG generated example designv6.1v7.0
(Xilinx Answer 62649)MIG UltraScale - GUI allows core generation even if all address and control byte lanes have not been selectedv6.0v7.0
(Xilinx Answer 60528)MIG UltraScale DDR3 - Vivado may fail to generate output products with 64-bit data widthv5.0v7.0
(Xilinx Answer 59991)MIG UltraScale - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful.v5.0v7.0
(Xilinx Answer 59989)MIG UltraScale - Critical warnings are generated when multiple MIG instances are included in a designv5.0v7.0
(Xilinx Answer 59990)MIG UltraScale - IPI MIG simulation does not have memory models availablev5.0v7.0
(Xilinx Answer 62321)MIG UltraScale DDR3/DDR4 - User Interface ports direction incorrect in instantiation templatev5.0v6.1
(Xilinx Answer 61988)MIG UltraScale DDR4/3 - Hold violations might be seen on a path clocked by riu_clkv6.0v6.1
(Xilinx Answer 62050)MIG UltraScale DDR4/3 - Can reset_n be allocated to an IO or does it have to be within a memory interface bank?v5.0v6.1
(Xilinx Answer 61909)MIG UltraScale DDR3/DDR4 - app_wdf_data format clarificationv6.0v6.1
(Xilinx Answer 61076)MIG UltraScale - Multiple instances of MIG IP fail with "[Place 30-678] Failed to do clock region partitioning"v5.0 Rev1v6.1
(Xilinx Answer 60953)MIG UltraScale - Output Products must be generated before opening the IP Example Designv5.0 Rev1v6.1
(Xilinx Answer 60181)MIG UltraScale DDR4/DDR3 - Timing violations may occur at higher data ratesv5.0v6.1
(Xilinx Answer 62080)MIG UltraScale DDR4 - AXI Narrow Burst simulations cause model warnings to be generatedv5.0v6.0
(Xilinx Answer 61901)MIG UltraScale DDR3/DDR4 - memory model violations observed during simulationv5.0 Rev1N/A
(Xilinx Answer 61725)MIG UltraScale DDR4 - Micron DDR4 part name shown in MIG GUI is obsoletev5.0 Rev1v6.0
(Xilinx Answer 61696)MIG UltraScale - the funcsim.v/.vhdl structural simulation model is not supportedv5.0 Rev1N/A
(Xilinx Answer 60322)MIG UltraScale DDR4 - MIG tool incorrectly allows Internal VREF to be disabled for DDR4 interfaces. Internal VREF is REQUIRED for all DDR4 interfaces.v5.0v1.1
(Xilinx Answer 59948)MIG UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact.
v5.0v5.0 Rev1

Revision History:

04/18/2017Created separate Answer record for DDR4
06/12/2017Updated for 2017.2; Added AR68028,AR69291


Associated Attachments

Name File Size File Type
memory_device_support_ddr4.xlsx 17 KB XLSX

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
69096 DDR4 UltraScale IP - DDR4 migration GUI not showing input skew value for cs[1] for ping pong PHY N/A N/A
AR# 69035
Date 06/20/2017
Status Active
Type Release Notes
  • Vivado Design Suite
  • MIG UltraScale
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