AR# 69035

UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the DDR4 UltraScale and UltraScale+ Cores and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

 

This Release Notes and Known Issues Answer Record is for the programmable logic DDR4 IP core supported in UltraScale and UltraScale+ based devices.

DDR4 IP Page

https://www.xilinx.com/products/intellectual-property/ddr4.htm

Xilinx Forums:

Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Solution

General Information:

 

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

 

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

DDR4 VersionVivado Tools Version
v2.2 (Rev. 9)2020.1
v2.2 (Rev. 8)2019.2
v2.2 (Rev. 7)2019.1
v2.2 (Rev. 6)2018.3
v2.2 (Rev. 5)2018.2
v2.2 (Rev. 4)2018.1
v2.2 (Rev. 3)2017.4
v2.2 (Rev. 2)2017.3
v2.2 (Rev. 1)2017.2
v2.22017.1
v2.1 (Rev. 1)2016.4
v2.12016.3
v2.0 (Rev. 1)2016.2
v2.02016.1
v1.12015.4
v1.02015.3
v7.12015.2
v7.02015.1
v6.12014.4
v6.02014.3
v5.0 (Rev. 1)2014.2
v5.02014.1

For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions Page.

For a complete list of supported DDR4 memory devices refer to the memory_device_support_ddr4.xlsx attachment found at the bottom of this Answer Record.

For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).

 

Known and Resolved Issues:


Table 2 provides the known and resolved issues for the UltraScale family DDR4 IP.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 2: Known and Resolved Issues

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 73715)UltraScale/UltraScale+ DDR3/DDR4 IP - Locked IPs using Self-Refresh with RDIMMs Must be Upgraded to Vivado 2020.1 or Later when Brought in to Vivado 2020.1 and Laterv2.2 (Rev. 9)NF
(Xilinx Answer 73714)UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardwarev2.2 (Rev. 9)NF
(Xilinx Answer 73068)Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions May Manifest as Post Calibration Data Errors or DQS Gate Tracking Errors in Hardwarev2.1 (Rev. 1)v2.2 (Rev. 9)
(Xilinx Answer 73052)UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] Phy Core Regeneration & Stitching Failedv1.0Not Resolved
(Xilinx Answer 72789)UltraScale/UltraScale+ DDR3/DDR4 IP - Usage Guidelines for Multiple High Frequency Save/Restore Cyclesv2.1NF
(Xilinx Answer 72582)UltraScale Memory IP - Space Grade Kintex UltraScale XQRKU060 Device Byte Planner Errors or MIG 66-99 Error in Bank 46 or Bank 25v2.2 (Rev. 7)
v2.2 (Rev. 9)
(Xilinx Answer 71778)UltraScale/UltraScale+ DDR4/DDR3 IP - Unable to Enter Self-Refresh when User Refresh is Enabledv2.2 (Rev. 4)
v2.2 (Rev. 7)
(Xilinx Answer 71696)UltraScale/UltraScale+ DDR4 - Add support for changing Refresh Parameters through Tcl flowv2.2 (Rev. 5)NAB
(Xilinx Answer 71531)UltraScale/UltraScale+ DDR4 DDR3 Post Save Restore ECC errors multi-rank onlyv2.1 (Rev. 1)v2.2 (Rev. 6)
(Xilinx Answer 70874)UltraScale/UltraScale+ DDR4 IP - AXI Arbitration ImprovementsV2.2v2.2 (Rev. 4)
(Xilinx Answer 69573)UltraScale/UltraScale+ DDR4 IP - 2017.x multi-controller designs fail calibration at WRITE_DQS_TO_DQ (complex) - IBUF_LOW_PWR attribute (2016.4 upgrade)V2.2v2.2 (Rev. 2)
(Xilinx Answer 69779)UltraScale/UltraScale+ DDR4 Address Parity incorrectly generated hen targeting 3DS RDIMMs and LRDIMMsv2.2 (Rev. 2)NF
(Xilinx Answer 69458)UltraScale DDR4 - JEDEC Spec Updates for tCK(avg) in Speed Bin Tables effects CL and CWL Values for DDR4-2133 and Higher Speed Grade Devicesv2.2 (Rev. 1)NF
(Xilinx Answer 69071)UltraScale/UltraScale+ DDR4/DDR3 IP - Simulations using UNISIM Models in NCSIM or using the ncinitialize Switch Gives Unexpected Resultsv2.1 (Rev. 1)NF
(Xilinx Answer 68997)UltraScale DDR4 - Unable to set data width to 80 for a x16 Wide Interface Component in custom CSVv2.2NF
(Xilinx Answer 68943)UltraScale DDR4 - MT40A1G16WBU-083E component with xcku115-flvb2104-2-e fails to generate output productsv2.2 (EA)v2.2 (Rev. 1)
(Xilinx Answer 67956)UltraScale/UltraScale+ DDR4/DDR3 - Supported configurations for Self Refresh and Save/Restorev2.1v2.2 (Rev. 1)
(Xilinx Answer 67979)UltraScale DDR4 - Design generation error occurs due to incorrect maximum MMCM VCO value for -1H speed gradev2.1NAB
(Xilinx Answer 66471)UltraScale DDR4 - Incorrect Write Recovery (WR) value programmed to Mode Register 0 (MR0)v1.1NF
(Xilinx Answer 68236)UltraScale DDR4 - upgrading locked IP might fail for select RDIMMsv2.1 (Rev. 1)NF
(Xilinx Answer 68143)UltraScale+ MPSoC DDR4 - Tactical Patch - IP GUI hangs and crashes for specific settingsv2.1v2.1 (Rev. 1)
(Xilinx Answer 67230)UltraScale DDR4 - tREFI interval is incorrectly setv2.0v2.1 (Rev. 1)
(Xilinx Answer 67891)UltraScale DDR4/DDR3 - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation modev2.0 (Rev. 1)v2.1
(Xilinx Answer 67631)UltraScale DDR4 - some parts use the incorrect memory speed gradev2.0 (Rev. 1)v2.1
(Xilinx Answer 67455)UltraScale DDR3/DDR4 - Tactical Patch - ECC signals are missing from the User Interface when ECC is enabled without AXIv2.0 (Rev. 1)v2.1
(Xilinx Answer 67255)UltraScale/UltraScale+ DDR4 - [Place 30-487] error may occur for some configurationsv2.0v2.1
(Xilinx Answer 67008)UltraScale DDR4 - Enabling DBI Read causes Read Complex register values in XSDB BRAM to not be populatedv2.0v2.1
(Xilinx Answer 66937)UltraScale/UltraScale+ DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore optionsv2.0NAB
(Xilinx Answer 66938)UltraScale+ DDR4 - Usage of six or more DDP (Dual Die Package/Twin Die) components is limited to 2133Mbps operationv2.0v2.1
(Xilinx Answer 67544)UltraScale DDR4/DDR3 - Tactical Patch - Data errors seen at user interface when using Normal Ordering Errorv2.0v2.1
(Xilinx Answer 67054)UltraScale/UltraScale+ DDR4 - Extra CK/CK# clock pair generated for some RDIMMs and LRDIMMsv2.0v2.1
(Xilinx Answer 66927)UltraScale DDR4/DDR3 - BFM simulations have errors when using Self Refresh and Self Restore optionsv2.0v2.0 (Rev. 1)
(Xilinx Answer 66560)UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Componentv1.1v2.0
(Xilinx Answer 66554)UltraScale+ DDR4 - a 300MHz reference input clock cannot be chosen for 1333MHz (750ps) output clock frequencyv2.0v2.0 (Rev. 1)
(Xilinx Answer 65083)UltraScale+ MPSoC DDR4/DDR3 - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 packagev1.0v2.0 (Rev. 1)
(Xilinx Answer 64774)UltraScale DDR4 - SETUP/HOLD violations in the mmcm_clkout0 domainv7.0v2.0
(Xilinx Answer 65950)UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs can fail in calibrationv1.0v2.0
(Xilinx Answer 65372)UltraScale DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulatorv1.0v2.0
(Xilinx Answer 64784)UltraScale DDR4 - false DRC MIG-32# errors detected for sys_clk_p/nv7.0v2.0
(Xilinx Answer 64856)Design Advisory for UltraScale DDR4/DDR3 - PCB pull-down required on the DDR3 RESET# pin and on the DDR4 RESET_N pin to maintain logic low during memory initializationv5.0v7.1
(Xilinx Answer 65790)UltraScale DDR4/DDR3 - Tactical Patch - when using a Custom Memory part some timing parameters are not updated correctlyv1.0v1.1
(Xilinx Answer 65652)UltraScale DDR3/DDR4 - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Write commandsv1.0v1.1
(Xilinx Answer 65493)UltraScale DDR4/DDR3 - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banksv1.0v1.1
(Xilinx Answer 63667)UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Modelv7.0v2.0
(Xilinx Answer 62086)UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mappingv5.0 (Rev. 1)v2.0
(Xilinx Answer 65261)UltraScale DDR4/DDR3 - Tactical Patch - Dynamic DCI does not work for some devicesv7.1v1.0
(Xilinx Answer 65054)UltraScale DDR4 - CAS Latency setting of 17 results in calibration failures during DQS Gate Calibrationv7.1v1.0
(Xilinx Answer 64887)UltraScale DDR4/DDR3 -Tactical Patch - Errors occur when implementing a 2015.1 MIG (v7.0) IP in Vivado 2015.2v7.0v1.0
(Xilinx Answer 64773)UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IPv7.0v1.0
(Xilinx Answer 64615)UltraScale DDR4/DDR3 - AXI Interface efficiency improvements for 2015.2v7.0v7.1
(Xilinx Answer 64306)UltraScale DDR4 - Tactical Patch -
Required calibration patch to resolve potential hardware failures due to incorrect DLL Reset during SDRAM initialization sequence (all configurations) and internal nibble clocking (x4 only)
v7.0v7.1
(Xilinx Answer 64010)UltraScale DDR4/DDR3 - memory controller can hang when in "Strict" modev7.0v7.1
(Xilinx Answer 64063)UltraScale DDR4/DDR3 - DIMM tool tip incorrectly lists the density for the base component partv7.0v7.1
(Xilinx Answer 63786)UltraScale DDR4 - SPEC_VIOLATION tWR/tRTP tWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Modelv7.0v7.0
(Xilinx Answer 63666)UltraScale DDR4 - tCK SPEC_VIOLATIONs for tCK = 833ps and speed bin = 833 when using Micron Memory Modelv7.0v7.0
(Xilinx Answer 63596)UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1v6.1v7.0
(Xilinx Answer 63261)UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT checkv6.1v7.0
(Xilinx Answer 63240)UltraScale DDR4/DDR3 - PHY Only Documentation - (PG150) includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation)v6.1v7.0
(Xilinx Answer 62930)UltraScale DDR4/DDR3 -Tactical Patch - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurationsv6.1v7.0
(Xilinx Answer 63022)UltraScale DDR4/DDR3 - Designs targeting dual rank DIMMs with address mirroring fail in hardwarev6.0v7.0
(Xilinx Answer 62776)UltraScale DDR4/DDR3 - ECC fault injection does not workv6.1v7.0
(Xilinx Answer 60528)UltraScale DDR4/DDR3 - Vivado may fail to generate output products with 64-bit data widthv5.0v7.0
(Xilinx Answer 62321)UltraScale DDR4/DDR3 - User Interface ports direction incorrect in instantiation templatev5.0v6.1
(Xilinx Answer 61988)UltraScale DDR4/DDR3 - Hold violations may be seen on a path clocked by riu_clkv6.0v6.1
(Xilinx Answer 62050)UltraScale DDR4/DDR3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank?v5.0v6.1
(Xilinx Answer 61909)UltraScale DDR3/DDR4 - app_wdf_data format clarificationv6.0v6.1
(Xilinx Answer 60181)UltraScale DDR4/DDR3 - Timing violations may occur at higher data ratesv5.0v6.1
(Xilinx Answer 62080)UltraScale DDR4 - AXI Narrow Burst simulations cause model warnings to be generatedv5.0v6.0
(Xilinx Answer 61901)UltraScale DDR3/DDR4 - memory model violations observed during simulationv5.0 (Rev. 1)NAB
(Xilinx Answer 61725)UltraScale/UltraScale+ DDR4 - Micron DDR4 part name shown in MIG GUI is obsoletev5.0 (Rev. 1)v6.0
(Xilinx Answer 60322)UltraScale DDR4 - MIG tool incorrectly allows Internal VREF to be disabled for DDR4 interfaces.v5.0v1.1
(Xilinx Answer 59948)UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact.v5.0v5.0 (Rev. 1)

Revision History:

 

04/18/2017Created separate Answer record for DDR4
06/12/2017Updated for 2017.2; Added (Xilinx Answer 68028),(Xilinx Answer 69291)
06/22/2017Added (Xilinx Answer 69324)
07/13/2017Added (Xilinx Answer 69458)
07/31/2017Updated debugging link to (Xilinx Answer 68937)
09/18/2017Updated AR formatting and linked (Xilinx Answer 69573)
11/29/2017Updated for 2017.4
03/13/2018Updated for 2018.1
04/04/2018Added AR70874
09/20/2018Updated for 2018.3
01/23/2019Added AR71531; Added AR71778
05/02/2019Updated for 2019.1
09/19/2019Added (Xilinx Answer 72789( and (Xilinx Answer 72582), Updated for 2019.2
11/04/2019Added AR7169; Added AR69071
11/19/2019Added AR73052
03/26/2020Added DAAR73068
05/27/2020Added AR73714; Added AR73715; Updated for 2020.1

Attachments

Associated Attachments

Name File Size File Type
memory_device_support_ddr4.xlsx 20 KB XLSX

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
69096 DDR4 UltraScale IP - DDR4 migration GUI not showing input skew value for cs[1] for ping pong PHY N/A N/A
69458 UltraScale DDR4 - JEDEC Spec Updates for tCK(avg) in Speed Bin Tables affects CL and CWL Values for DDR4-2133 and Higher Speed Grade Devices N/A N/A
68997 UltraScale DDR4 - Unable to set data width to 80 for a x16 Wide Interface Component in custom CSV N/A N/A
68943 UltraScale DDR4 - MT40A1G16WBU-083E component with xcku115-flvb2104-2-e fails to generate output products N/A N/A
67956 UltraScale/UltraScale+ DDR4/DDR3 - Supported configurations for Self Refresh and Save/Restore N/A N/A
67979 UltraScale DDR4 - Design generation error occurs due to incorrect maximum MMCM VCO value for -1H speed grade N/A N/A
66471 UltraScale/UltraScale+ DDR4 IP - Incorrect Write Recovery (WR) value programmed to Mode Register 0 (MR0) N/A N/A
68236 UltraScale DDR4 - upgrading locked IP might fail for select RDIMMs N/A N/A
68143 UltraScale+ MPSoC DDR4 - Tactical Patch - IP GUI hangs and crashes for specific settings N/A N/A
67230 UltraScale DDR4 - tREFI interval is incorrectly set N/A N/A
67891 UltraScale DDR4/DDR3 - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode N/A N/A
67631 UltraScale DDR4 - some parts use the incorrect memory speed grade N/A N/A
67455 UltraScale DDR3/DDR4 - Tactical Patch - ECC signals are missing from the User Interface when ECC is enabled without AXI N/A N/A
67255 UltraScale/UltraScale+ DDR4 - [Place 30-487] error may occur for some configurations N/A N/A
67008 UltraScale DDR4 - Enabling DBI Read causes Read Complex register values in XSDB BRAM to not be populated N/A N/A
66938 UltraScale+ DDR4 - Usage of six or more DDP (Dual Die Package/Twin Die) components is limited to 2133Mbps operation N/A N/A
67544 UltraScale DDR4/DDR3 - Tactical Patch - Data errors seen at user interface when using Normal Ordering Error N/A N/A
67054 UltraScale/UltraScale+ DDR4 - Extra CK/CK# clock pair generated for some RDIMMs and LRDIMMs N/A N/A
66927 UltraScale DDR4/DDR3 - BFM simulations have errors when using Self Refresh and Self Restore options N/A N/A
66554 UltraScale+ DDR4 - a 300MHz reference input clock cannot be chosen for 1333MHz (750ps) output clock frequency N/A N/A
65083 UltraScale+ MPSoC DDR4/DDR3 - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 package N/A N/A
64774 UltraScale DDR4 - SETUP/HOLD violations in the mmcm_clkout0 domain N/A N/A
65950 UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs can fail in calibration N/A N/A
61725 MIG UltraScale DDR4 - Micron DDR4 part name shown in MIG GUI is obsolete N/A N/A
61901 UltraScale DDR3/DDR4 - memory model violations observed during simulation N/A N/A
60181 UltraScale DDR4/DDR3 - Timing violations can occur at higher data rates N/A N/A
61909 UltraScale DDR3/DDR4 - app_wdf_data format clarification N/A N/A
61988 UltraScale DDR4/DDR3 - Hold violations may be seen on a path clocked by riu_clk N/A N/A
62321 UltraScale DDR4/DDR3 - User Inteface ports direction incorrect in instantiation template N/A N/A
60528 UltraScale DDR4/DDR3 - Vivado might fail to generate output products with 64-bit data width N/A N/A
63261 UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT check N/A N/A
62776 UltraScale DDR4/DDR3 - ECC fault injection does not work N/A N/A
63022 UltraScale DDR4/DDR3 - Designs targeting dual rank DIMMs with address mirroring fail in hardware N/A N/A
62930 UltraScale DDR4/DDR3 -Tactical Patch - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurations N/A N/A
63240 MIG UltraScale DDR4/DDR3 - PHY Only Documentation - (PG150) includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation) N/A N/A
63596 UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1 N/A N/A
63666 UltraScale DDR4 - tCK SPEC_VIOLATIONs for tCK = 833ps and speed bin = 833 when using Micron Memory Model N/A N/A
63786 UltraScale DDR4 - SPEC_VIOLATION tWR/tRTP tWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model N/A N/A
64063 UltraScale DDR4/DDR3 - DIMM tool tip incorrectly lists the density for the base component part N/A N/A
64010 UltraScale DDR4/DDR3 - memory controller can hang when in "Strict" mode N/A N/A
64773 MIG UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IP N/A N/A
64887 UltraScale DDR4/DDR3 -Tactical Patch - Errors occur when implementing a 2015.1 MIG (v7.0) IP in Vivado 2015.2 N/A N/A
65261 UltraScale DDR4/DDR3 - Tactical Patch - Dynamic DCI does not work for some devices N/A N/A
63667 UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model N/A N/A
65652 UltraScale DDR3/DDR4 - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Write commands N/A N/A
65790 UltraScale DDR4/DDR3 - Tactical Patch - when using a Custom Memory part some timing parameters are not updated correctly N/A N/A
64784 UltraScale DDR4 - false DRC MIG-32# errors detected for sys_clk_p/n N/A N/A
65372 UltraScale DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulator N/A N/A
59948 UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact. N/A N/A
60322 UltraScale DDR4 - MIG tool incorrectly allows Internal VREF to be disabled for DDR4 interfaces. N/A N/A
62080 UltraScale DDR4 - AXI Narrow Burst simulations cause model warnings to be generated N/A N/A
62050 UltraScale DDR4/DDR3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank? N/A N/A
64306 UltraScale DDR4 - Tactical Patch - Required calibration patch to resolve potential hardware failures due to incorrect DLL Reset during SDRAM initialization sequence (all configurations) and internal nibble clocking (x4 only) N/A N/A
64615 UltraScale DDR4/DDR3 - AXI Interface efficiency improvements for 2015.2 N/A N/A
65054 UltraScale DDR4 - CAS Latency setting of 17 results in calibration failures during DQS Gate Calibration N/A N/A
65493 UltraScale DDR4/DDR3 - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banks N/A N/A
66794 UltraScale DDR3 - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settings N/A N/A
69779 UltraScale/UltraScale+ DDR4 Address Parity support for RDIMMs, 3DS RDIMMs and LRDIMMs N/A N/A
69573 UltraScale/UltraScale+ DDR4 IP - 2017.x multi-controller designs fail calibration at WRITE_DQS_TO_DQ (complex) - IBUF_LOW_PWR attribute (2016.4 upgrade) N/A N/A
66937 UltraScale/UltraScale+ DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore options N/A N/A
66560 UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Component N/A N/A
70874 UltraScale/UltraScale+ DDR4 IP - AXI Arbitration Improvements N/A N/A
71696 UltraScale/UltraScale+ DDR4 - Add support for changing Refresh Parameters through Tcl flow N/A N/A
71697 UltraScale+ RFSoC DDR4/DDR3/RLDRAM3 - The FSVE1156 package allows incorrect data widths N/A N/A
71778 UltraScale/UltraScale+ DDR4/DDR3 IP - Unable to Enter Self-Refresh when User Refresh is Enabled N/A N/A
72789 UltraScale/UltraScale+ DDR3/DDR4 IP - Usage Guidelines for Multiple High Frequency Save/Restore Cycles N/A N/A
72582 UltraScale Memory IP - Space Grade Kintex UltraScale XQRKU060 Device Byte Planner Errors or MIG 66-99 Error in Bank 46 or Bank 25 N/A N/A
69071 UltraScale/UltraScale+ DDR4/DDR3 IP - Simulations using UNISIM Models in NCSIM or Using the ncinitialize Switch Gives Unexpected Results N/A N/A
73052 UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] Phy Core Regeneration and Stitching Failed N/A N/A
73068 Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions Might Manifest as Post Calibration Data Errors or DQS Gate Tracking Errors in Hardware N/A N/A
73714 UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardware N/A N/A
73715 UltraScale/UltraScale+ DDR3/DDR4 IP - Locked IPs using Self-Refresh with RDIMMs Must be Upgraded to Vivado 2020.1 or Later when Brought in to Vivado 2020.1 and Later N/A N/A
AR# 69035
Date 08/07/2020
Status Active
Type Release Notes
Devices More Less
Tools
IP