This answer record contains the Release Notes and Known Issues for the RLDRAM3 UltraScale and UltraScale+ cores and includes the following:
This Release Notes and Known Issues Answer Record is for the programmable logic RLDRAM3 IP core supported in UltraScale and UltraScale+ based devices.
RLDRAM3 IP Page:
Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
Supported devices can be found in the following locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|RLDRAM3 Version||Vivado Tools Version|
|v1.4 (Rev. 8)||2019.2|
|v1.4 (Rev. 7)||2019.1|
|v1.4 (Rev. 6)||2018.3|
|v1.4 (Rev. 5)||2018.2|
|v1.4 (Rev. 4)||2018.1|
|v1.4 (Rev. 3)||2017.4|
|v1.4 (Rev. 2)||2017.3|
|v1.4 (Rev. 1)||2017.2|
|v1.3 (Rev. 1)||2016.4|
|v1.2 (Rev. 1)||2016.2|
|v5.0 (Rev. 1)||2014.2|
For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page.
For a complete list of supported RLDRAM3 memory devices refer to the memory_device_support_rldram3.xlsx attachment found at the bottom of this Answer Record.
For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).
Known and Resolved Issues
Table 2 provides a list of post-2015.1 MIG UltraScale RLDRAM3 IP patches that are recommended be installed if currently in production but are unable to upgrade the IP to 2016.1.
All other users are recommended to upgrade to 2016.1.
Table 3 provides the known and resolved issues for the UltraScale family RLDRAM3 IP.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 2: RLDRAM3 IP Patches
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 69438)||UltraScale/UltraScale+ RLDRAM3 IP v1.4 - Vivado 2016.4 and 2017.x - Previously working interface now fails calibration at Write DQ/DM Deskew step||v1.4||N/A|
|(Xilinx Answer 70214)||UltraScale/UltraScale+ - RLDRAM3 IP - Tactical Patch for SEM and RLD integration||v1.3||N/A|
|(Xilinx Answer 66689)||UltraScale RLDRAM3 IP - patch update recommended for 2015.4||v1.1||v2.0|
|(Xilinx Answer 66688)||UltraScale RLDRAM3 IP - patch update recommended for 2015.3||v1.0||v2.0|
|(Xilinx Answer 66035)||MIG UltraScale RLDRAM3 IP - patch update recommended for 2015.2||v7.1||v2.0|
|(Xilinx Answer 66034)||MIG UltraScale RLDRAM3 IP - patch update recommended for 2015.1||v7.0||v2.0|
Table 3: Known and Resolved Issues
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 72230)||UltraScale/UltraScale+ - RLDRAM3 IP - Known Issues with RLDRAM3 and SEM IP Interaction||v1.3||No Plan To Fix|
|(Xilinx Answer 67922)||UltraScale RLDRAM3 - Advanced Traffic Generator (ATG) detects data compare errors when testing with the TG_MAX_NUM_OF_ITER_ADDR parameter is set to a large value||v1.2 (Rev. 1)||NAB|
|(Xilinx Answer 67367)||UltraScale RLDRAM3 - when targeting 576Mb and 1.125Gb x36 parts an extra address bit exists on the pin out||v1.2||v1.3|
|(Xilinx Answer 67125)||UltraScale RLDRAM3 - spec violation allowed for Read Latency (RL) of 15 and -107 speed bin||v1.2||v1.2 (Rev. 1)|
|(Xilinx Answer 66589)||UltraScale RLDRAM3 - ERROR: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed.||v1.1||v1.2|
|(Xilinx Answer 65371)||UltraScale RLDRAM3 - hardware failures can occur at lower frequencies of operation||v1.0||v1.2|
|(Xilinx Answer 65787)||UltraScale RLDRAM3 - Calibration failures can occur when Data Mask (DM) is disabled||v1.0||v1.1|
|(Xilinx Answer 65651)||UltraScale RLDRAM3 - Read Latency of 17 is not a valid value for "-093E' parts||v1.0||v1.1|
|(Xilinx Answer 65219)||UltraScale RLDRAM3 - older versions of MIG UltraScale RLDRAM IP cause critical warnings in 2015.3||v1.0||No Plan To Fix|
|(Xilinx Answer 64946)||UltraScale RLDRAM3 - PCB pull-down required on RESET#||v7.1||v1.0|
|(Xilinx Answer 64772)||UltraScale RLDRAM3 - timing failures in mmcm_clk0 domain as a result of too many logic levels||v7.1||v1.0|
|(Xilinx Answer 64486)||UltraScale RLDRAM3 - tWTR violations seen at frequencies greater than 750MHz||v7.0||v1.0|
|(Xilinx Answer 64642)||UltraScale RLDRAM3 - IP upgrade in 2015.1 creates DDR4 controller||v7.0||v7.1|
|(Xilinx Answer 62593)||UltraScale RLDRAM3 - default bank selection for 72-bit designs fails to select all data byte lanes||v6.0||v7.0|
|(Xilinx Answer 63596)||UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1||v6.1||v7.0|
|(Xilinx Answer 63687)||UltraScale RLDRAM3 - IDELAY taps do not move during QVLD Calibration which can cause data errors in hardware||v6.1||v7.0|
|(Xilinx Answer 63238)||UltraScale RLDRAM3 - Tactical Patch - timing failures in mmcm_clkout0 domain||v6.1||v7.0|
|(Xilinx Answer 61627)||UltraScale RLDRAM3 - data mask does not work for RLDRAM3 designs||v5.0 (Rev .1)||v6.0|
|(Xilinx Answer 60951)||UltraScale RLDRAM3/QDRII+ - Timing failure from XiPHY to riu_clk||v5.0 (Rev. 1)||v6.0|
|04/18/2017||Created Separate Answer Record for RLDRAM3|
|06/12/2017||Updated for 2017.2; Added AR68028, AR69291|
|07/31/2017||Updated debugging link to AR#68937|
|09/18/2017||Updated formatting and updated for 2017.3|
|11/29/2017||Updated for 2017.4|
|03/13/2018||Updated for 2018.1|
|09/20/2018||Updated for 2018.3|
|05/02/2019||Updated for 2019.1; Added AR#72230|
|10/21/2019||Updated for 2019.2|
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