AR# 69039


UltraScale/UltraScale+ QDRIV IP - Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the QDRIV UltraScale and UltraScale+ cores and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the programmable logic QDRIV IP core supported in UltraScale and UltraScale+ based devices.


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Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support. 

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General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

QDRIV VersionVivado Tools Version
v2.0 (Rev. 9)2020.1
v2.0 (Rev. 8)2019.2
v2.0 (Rev. 7)2019.1
v2.0 (Rev. 6)2018.3
v2.0 (Rev. 5)2018.2
v2.0 (Rev. 4)2018.1
v2.0 (Rev. 3)2017.4
v2.0 (Rev. 2)2017.3
v2.0 (Rev. 1)2017.2
v1.2 (Rev. 1)2016.4
v1.1 (Rev. 1)2016.2

For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page:

For a complete list of supported QDRIV memory devices refer to the memory_device_support_qdriv.xlsx attachment found at the bottom of this Answer Record.

For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).

Known and Resolved Issues

Table 2 provides the known and resolved issues for the UltraScale family QDRIV IP.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 2: Known and Resolved Issues

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 73714)UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardwarev2.0 (Rev. 9)NF
(Xilinx Answer 70193)UltraScale/UltraScale+ QDRIV IP v2.0 - Hold violationsv1.2v2.0 (Rev. 4)
(Xilinx Answer 68037)UltraScale/UltraScale+ QDRIV IP - vio_tg_start is Unconnected to Advanced Traffic Generator (ATG)v1.2v2.0 (Rev. 4)
(Xilinx Answer 65395)UltraScale/UltraScale+ QDRIV IP - "UNKNOWN STATE ERROR" Messages Reported During Simulations when using QuestaSimv1.0v1.1

Revision History:
04/18/2017Created separate Answer Record for QDRIV
06/12/2017Updated for 2017.2
07/31/2017Updated debugging link to (Xilinx Answer 68937)
08/31/2017Removed generic AR link and updated AR formatting
09/18/2017Updated for 2017.3
12/07/2017Added (Xilinx Answer 70193) and updated for 2017.4
03/13/2018Updated for 2018.1
09/20/2018Updated for 2018.3
05/02/2019Updated for 2019.1
10/20/2019Updated for 2019.2
05/21/2020Added AR#73714; Updated for 2020.1


Associated Attachments

Name File Size File Type
memory_device_support_qdriv.xlsx 18 KB XLSX

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AR# 69039
Date 06/10/2020
Status Active
Type Release Notes
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