AR# 6905: 12.1 Constraints - How do I apply a PERIOD constraint on a DLL/DCM/PLL/MMCM?
12.1 Constraints - How do I apply a PERIOD constraint on a DLL/DCM/PLL/MMCM?
How do I apply a PERIOD timing specification using a DLL, PLL, DCM, or MMCM? For more information, see (Xilinx Answer 2586).
When a TNM_NET property is traced into the CLKIN pin of a DLL, PLL, DCM, or MMCM component, the TNM group and its usage are examined. The TNM is pushed through the CLKDLL only if the following conditions are met: - The TNM group name is used in exactly one PERIOD specification. - The TNM group name is not used in any FROM:TO or OFFSET specifications. - The TNM group name is not referenced in any user group definition. If any of the above conditions are not met, the TNM is not pushed through the DCM/PLL/DLL, and the following error message occurs: "ERROR:NgdHelpers:702 - The TNM "PAD_CLK" drives the CLKIN pin of CLKDLL "$I1". This TNM cannot be traced through the CLKDLL/DCM/PLL because it is not used in exactly one PERIOD specification. This TNM is used in the following user groups and/or specifications: TS_PAD_CLK=PERIOD PAD_CLK 20000.000000 pS HIGH 50.000000% TS_01=FROM PAD_CLK TO PADS 20000.000000 pS" If the above conditions are met, each clock output pin on the DCM/PLL/DLL/MMCM is examined to see if it is connected to a net with at least one other connection (i.e., it is not a dangling net). If the output pin has a net, a new TNM group is created on that net, and a new PERIOD specification is created for that group. The new specification is copied from the original PERIOD specification, and then modified as follows. Modifications to PERIOD Specification with Respect to the Following Output Pins CLK0: See Note below. CLK90: See Note below. CLK180: See Note below. CLK270: See Note below. CLK2X: The PERIOD value is doubled (if originally expressed as a frequency) or divided in half (if originally expressed as a delay). The duty cycle is also adjusted to 50%. CLKDV: The PERIOD value is divided (if a frequency) or multiplied (if a delay) by the value in the CLKDV_DIVIDE property. If this property is not found on or above the CLKDLL, the default value of 2.0 is used. The duty cycle is also adjusted to 50%. NOTE: If the DUTY_CYCLE_CORRECTION=TRUE property is found on or above the CLKDLL, the duty cycle is adjusted to 50%. If DUTY_CYCLE_CORRECTION=FALSE is found, the duty cycle is unchanged from the original PERIOD specification. If no DUTY_CYCLE_CORRECTION property is found, the default value of TRUE is assumed. If the original TNM_NET property is pushed only into the CLKDLL CLKIN pin (i.e., it does not trace to any appropriate elements without going through the CLKDLL), the original TNM group and the original PERIOD specification are eliminated from the design. If a newly-created TNM group is pushed forward from a CLKDLL output and encounters the CLKIN input of a second CLKDLL (such as in the 4X configuration), the above process is repeated to further adjust the PERIOD specification(s) per the behavior of the second CLKDLL. If the group created for the first CLKDLL traces only into the second CLKDLL, that group and its PERIOD specification become unnecessary and are eliminated. For more information on property tracing through the CLKDLL, refer to the "Constraints Guide": http://www.xilinx.com/support/software_manuals.htm For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf