In CPRI cores supporting 24,330.24 Mbps line rate and FEC Enabled Mode, 64B/66B scrambling is not enabled on the following FEC line rates.
All other line rates are unaffected.
The CPRI core will work as expected using FEC enabled line rates while in loopback mode, and in systems where both master and slave use the same Xilinx CPRI core.
However, it will not be compatible with non-Xilinx CPRI cores using 64B/66B scrambling at FEC Enabled line rates.
This is a known issue in the CPRI v8.7 (Rev 2) core, included in the 2017.1 Vivado release. It will be fixed in the 2017.2 release.
It affects cores supporting 24,330.24 Mbps line rate and FEC Enabled Mode only.
For other CPRI known issues, please refer to (Xilinx Answer 54473)