2. Support
  3. AR# 6905: 12.1 Constraints - How do I apply a PERIOD constraint on a DLL/DCM/PLL/MMCM?
  4. AR# 69057: LogiCORE IP MIPI D-PHY v3.0 (Rev. 1) - Why is an SOTsynchs error generated from the MIPI DPHY RX IP or MIPI CSI-2 RX Subsystem?

AR# 69057

LogiCORE IP MIPI D-PHY v3.0 (Rev. 1) - Why is an SOTsynchs error generated from the MIPI DPHY RX IP or MIPI CSI-2 RX Subsystem?

Description

I am seeing frequent SOTSynchs errors generated from the MIPI DPHY RX IP or the MIPI CSI-2 RX Subsystem.

I am also observing data skew between data lanes and noise data from the IP in the ILA data.

The MIPI D-PHY IP detects noise data as SOT(0xB8) and generates an SOTSynchs error in this case.

Solution

The C_HS_SETTLE_NS parameter in the MIPI DPHY IP can be increased to ignore noise data. This value is hidden in the 2016.4 version, but has been made available for users to edit in the 2017.1 release.

After updating the IP, you can increase the value of the C_HS_SETTLE_NS register available at the MIPI DPHY Registers address offset of 0x30 through the register interface.

Note: The Unit are in nanoseconds (ns) i.e. 180ns = 0xB4h.

If you are using the 2016.4 version, you can download the LogiCORE IP MIPI D-PHY v3.0 (Rev. 1) patch from (Xilinx Answer 68810) to work around this issue.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
65242 MIPI CSI-2 Receiver Subsystem - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
54550 LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
68810 2016.4 LogiCORE IP MIPI D-PHY v3.0 (Rev. 1) - Patch Updates for the LogiCORE IP MIPI D-PHY v3.0 (Rev. 1) N/A N/A
AR# 69057
Date 04/24/2018
Status Archive
Type General Article
Devices
IP