AR# 69108


2017.1 Zynq UltraScale+ MPSoC: xilpm library fails to build


In hardware designs where R5_1 is not assigned an IP Integrator slot, the xilpm library fails to build. This results in breakage of the FSBL build because xilpm is used by the FSBL.


By default, R5_1 is assigned an IP Integrator slot unless the user chooses to change it in the advanced processor config GUI in Vivado.

The suggested work-around is to not change the default IP Integrator settings, and in cases where it needs to be changed, ensure that APU, R5_0 and R5_1 are assigned at least one IP Integrator slot each.

AR# 69108
Date 08/21/2017
Status Active
Type Known Issues
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